Merge branch 'u-boot-ti/master' into 'u-boot-arm/master'

[karo-tx-uboot.git] / board / ti / dra7xx / mux_data.h

diff --git a/board/ti/dra7xx/mux_data.h b/board/ti/dra7xx/mux_data.h
index 04c95fd376ac4fbdee5a8e43b6a3c6a7909af903..7db70324e9bc78a5d301bbbb1f75331969e77451 100644 (file)
--- a/board/ti/dra7xx/mux_data.h
+++ b/board/ti/dra7xx/mux_data.h
@@ -5,23 +5,7 @@
  * Sricharan R <r.sricharan@ti.com>
  * Nishant Kamat <nskamat@ti.com>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 #ifndef _MUX_DATA_DRA7XX_H_
 #define _MUX_DATA_DRA7XX_H_
@@ -29,19 +13,71 @@
 #include <asm/arch/mux_dra7xx.h>
 
 const struct pad_conf_entry core_padconf_array_essential[] = {
-       {MMC1_CLK, (PTU | IEN | M0)},   /* MMC1_CLK */
-       {MMC1_CMD, (PTU | IEN | M0)},   /* MMC1_CMD */
-       {MMC1_DAT0, (PTU | IEN | M0)},  /* MMC1_DAT0 */
-       {MMC1_DAT1, (PTU | IEN | M0)},  /* MMC1_DAT1 */
-       {MMC1_DAT2, (PTU | IEN | M0)},  /* MMC1_DAT2 */
-       {MMC1_DAT3, (PTU | IEN | M0)},  /* MMC1_DAT3 */
-       {MMC1_SDCD, (PTU | IEN | M0)},  /* MMC1_SDCD */
-       {MMC1_SDWP, (PTU | IEN | M0)},  /* MMC1_SDWP */
-       {UART1_RXD, (PTU | IEN | M0)},  /* UART1_RXD */
-       {UART1_TXD, (M0)},              /* UART1_TXD */
-       {UART1_CTSN, (PTU | IEN | M0)}, /* UART1_CTSN */
-       {UART1_RTSN, (M0)},             /* UART1_RTSN */
-       {I2C1_SDA, (PTU | IEN | M0)},   /* I2C1_SDA */
-       {I2C1_SCL, (PTU | IEN | M0)},   /* I2C1_SCL */
+       {MMC1_CLK, (IEN | PTU | PDIS | M0)},    /* MMC1_CLK */
+       {MMC1_CMD, (IEN | PTU | PDIS | M0)},    /* MMC1_CMD */
+       {MMC1_DAT0, (IEN | PTU | PDIS | M0)},   /* MMC1_DAT0 */
+       {MMC1_DAT1, (IEN | PTU | PDIS | M0)},   /* MMC1_DAT1 */
+       {MMC1_DAT2, (IEN | PTU | PDIS | M0)},   /* MMC1_DAT2 */
+       {MMC1_DAT3, (IEN | PTU | PDIS | M0)},   /* MMC1_DAT3 */
+       {MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */
+       {MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */
+       {GPMC_A19, (IEN | PTU | PDIS | M1)},    /* mmc2_dat4 */
+       {GPMC_A20, (IEN | PTU | PDIS | M1)},    /* mmc2_dat5 */
+       {GPMC_A21, (IEN | PTU | PDIS | M1)},    /* mmc2_dat6 */
+       {GPMC_A22, (IEN | PTU | PDIS | M1)},    /* mmc2_dat7 */
+       {GPMC_A23, (IEN | PTU | PDIS | M1)},    /* mmc2_clk */
+       {GPMC_A24, (IEN | PTU | PDIS | M1)},    /* mmc2_dat0 */
+       {GPMC_A25, (IEN | PTU | PDIS | M1)},    /* mmc2_dat1 */
+       {GPMC_A26, (IEN | PTU | PDIS | M1)},    /* mmc2_dat2 */
+       {GPMC_A27, (IEN | PTU | PDIS | M1)},    /* mmc2_dat3 */
+       {GPMC_CS1, (IEN | PTU | PDIS | M1)},    /* mmm2_cmd */
+#if (CONFIG_CONS_INDEX == 1)
+       {UART1_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_RXD */
+       {UART1_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_TXD */
+       {UART1_CTSN, (IEN | PTU | PDIS | M3)},  /* UART1_CTSN */
+       {UART1_RTSN, (IEN | PTU | PDIS | M3)},  /* UART1_RTSN */
+#elif (CONFIG_CONS_INDEX == 3)
+       {UART3_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_RXD */
+       {UART3_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART3_TXD */
+#endif
+       {I2C1_SDA, (IEN | PTU | PDIS | M0)},    /* I2C1_SDA */
+       {I2C1_SCL, (IEN | PTU | PDIS | M0)},    /* I2C1_SCL */
+       {MDIO_MCLK, (PTU | PEN | M0)},          /* MDIO_MCLK  */
+       {MDIO_D, (IEN | PTU | PEN | M0)},       /* MDIO_D  */
+       {RGMII0_TXC, (M0) },
+       {RGMII0_TXCTL, (M0) },
+       {RGMII0_TXD3, (M0) },
+       {RGMII0_TXD2, (M0) },
+       {RGMII0_TXD1, (M0) },
+       {RGMII0_TXD0, (M0) },
+       {RGMII0_RXC, (IEN | M0) },
+       {RGMII0_RXCTL, (IEN | M0) },
+       {RGMII0_RXD3, (IEN | M0) },
+       {RGMII0_RXD2, (IEN | M0) },
+       {RGMII0_RXD1, (IEN | M0) },
+       {RGMII0_RXD0, (IEN | M0) },
+       {VIN2A_D12, (M3) },
+       {VIN2A_D13, (M3) },
+       {VIN2A_D14, (M3) },
+       {VIN2A_D15, (M3) },
+       {VIN2A_D16, (M3) },
+       {VIN2A_D17, (M3) },
+       {VIN2A_D18, (IEN | M3)},
+       {VIN2A_D19, (IEN | M3)},
+       {VIN2A_D20, (IEN | M3)},
+       {VIN2A_D21, (IEN | M3)},
+       {VIN2A_D22, (IEN | M3)},
+       {VIN2A_D23, (IEN | M3)},
+       {GPMC_A13, (IEN | PDIS | M1)},  /* QSPI1_RTCLK */
+       {GPMC_A14, (IEN | PDIS | M1)},  /* QSPI1_D[3] */
+       {GPMC_A15, (IEN | PDIS | M1)},  /* QSPI1_D[2] */
+       {GPMC_A16, (IEN | PDIS | M1)},  /* QSPI1_D[1] */
+       {GPMC_A17, (IEN | PDIS | M1)},  /* QSPI1_D[0] */
+       {GPMC_A18, (M1)},  /* QSPI1_SCLK */
+       {GPMC_A3, (IEN | PDIS | M1)},   /* QSPI1_CS2 */
+       {GPMC_A4, (IEN | PDIS | M1)},   /* QSPI1_CS3 */
+       {GPMC_CS2, (IEN | PTU | PDIS | M1)},    /* QSPI1_CS0 */
+       {GPMC_CS3, (IEN | PTU | PDIS | M1)},    /* QSPI1_CS1*/
+       {USB2_DRVVBUS, (M0 | IEN | FSC) },
 };
 #endif /* _MUX_DATA_DRA7XX_H_ */