Merge branch 'master' of git://git.denx.de/u-boot-arm

[karo-tx-uboot.git] / board / ti / ks2_evm / ddr3_k2hk.c

diff --git a/board/ti/ks2_evm/ddr3_k2hk.c b/board/ti/ks2_evm/ddr3_k2hk.c
index 21a5a0a252e5096b9bbd4dbfb7873b3e781736e9..a1c3d05f8e50e2f7d4f2a62097f8e46379f0aaaa 100644 (file)
--- a/board/ti/ks2_evm/ddr3_k2hk.c
+++ b/board/ti/ks2_evm/ddr3_k2hk.c
@@ -12,6 +12,8 @@
 #include <asm/arch/ddr3.h>
 #include <asm/arch/hardware.h>
 
+static int ddr3_size;
+
 struct pll_init_data ddr3a_333 = DDR3_PLL_333(A);
 struct pll_init_data ddr3a_400 = DDR3_PLL_400(A);
 
@@ -44,12 +46,14 @@ void ddr3_init(void)
                        ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
                                          &ddr3_1600_8g);
                        printf("DRAM:  Capacity 8 GiB (includes reported below)\n");
+                       ddr3_size = 8;
                } else {
                        ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g);
                        ddr3_1600_8g.sdcfg |= 0x1000;
                        ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
                                          &ddr3_1600_8g);
                        printf("DRAM:  Capacity 4 GiB (includes reported below)\n");
+                       ddr3_size = 4;
                }
        } else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) {
                init_pll(&ddr3a_333);
@@ -70,15 +74,31 @@ void ddr3_init(void)
                        }
                        ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
                                          &ddr3_1333_2g);
+                       ddr3_size = 2;
+                       printf("DRAM:  2 GiB");
                } else {
                        ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_2g);
                        ddr3_1333_2g.sdcfg |= 0x1000;
                        ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE,
                                          &ddr3_1333_2g);
+                       ddr3_size = 1;
+                       printf("DRAM:  1 GiB");
                }
        } else {
                printf("Unknown SO-DIMM. Cannot configure DDR3\n");
                while (1)
                        ;
        }
+
+       /* Apply the workaround for PG 1.0 and 1.1 Silicons */
+       if (cpu_revision() <= 1)
+               ddr3_err_reset_workaround();
+}
+
+/**
+ * ddr3_get_size - return ddr3 size in GiB
+ */
+int ddr3_get_size(void)
+{
+       return ddr3_size;
 }