static int npe_used[NPE_NUM_PORTS];
/* A little extra so we can align to cacheline. */
-static u8 npe_alloc_pool[NPE_MEM_POOL_SIZE + CFG_CACHELINE_SIZE - 1];
+static u8 npe_alloc_pool[NPE_MEM_POOL_SIZE + CONFIG_SYS_CACHELINE_SIZE - 1];
static u8 *npe_alloc_end;
static u8 *npe_alloc_free;
static int count = 0;
void *p = NULL;
- size = (size + (CFG_CACHELINE_SIZE-1)) & ~(CFG_CACHELINE_SIZE-1);
+ size = (size + (CONFIG_SYS_CACHELINE_SIZE-1)) & ~(CONFIG_SYS_CACHELINE_SIZE-1);
count++;
if ((npe_alloc_free + size) < npe_alloc_end) {
p = npe_alloc_free;
npe_alloc_free += size;
} else {
- printf("%s: failed (count=%d, size=%d)!\n", count, size);
+ printf("npe_alloc: failed (count=%d, size=%d)!\n", count, size);
}
return p;
}
npe_alloc_end = npe_alloc_pool + sizeof(npe_alloc_pool);
npe_alloc_free = (u8 *)(((unsigned)npe_alloc_pool +
- CFG_CACHELINE_SIZE - 1) & ~(CFG_CACHELINE_SIZE - 1));
+ CONFIG_SYS_CACHELINE_SIZE - 1) & ~(CONFIG_SYS_CACHELINE_SIZE - 1));
/* initialize mbuf pool */
init_rx_mbufs(p_npe);
if (ixEthAccPortRxCallbackRegister(p_npe->eth_id, npe_rx_callback,
(u32)p_npe) != IX_ETH_ACC_SUCCESS) {
printf("can't register RX callback!\n");
- return 0;
+ return -1;
}
if (ixEthAccPortTxDoneCallbackRegister(p_npe->eth_id, npe_tx_callback,
(u32)p_npe) != IX_ETH_ACC_SUCCESS) {
printf("can't register TX callback!\n");
- return 0;
+ return -1;
}
npe_set_mac_address(dev);
if (ixEthAccPortEnable(p_npe->eth_id) != IX_ETH_ACC_SUCCESS) {
printf("can't enable port!\n");
- return 0;
+ return -1;
}
p_npe->active = 1;
- return 1;
+ return 0;
}
#if 0 /* test-only: probably have to deal with it when booting linux (for a clean state) */
int eth_num = 0;
struct npe *p_npe = NULL;
- for (eth_num = 0; eth_num < CFG_NPE_NUMS; eth_num++) {
+ for (eth_num = 0; eth_num < CONFIG_SYS_NPE_NUMS; eth_num++) {
/* See if we can actually bring up the interface, otherwise, skip it */
switch (eth_num) {
npe_alloc_end = npe_alloc_pool + sizeof(npe_alloc_pool);
npe_alloc_free = (u8 *)(((unsigned)npe_alloc_pool +
- CFG_CACHELINE_SIZE - 1)
- & ~(CFG_CACHELINE_SIZE - 1));
+ CONFIG_SYS_CACHELINE_SIZE - 1)
+ & ~(CONFIG_SYS_CACHELINE_SIZE - 1));
if (!npe_csr_load())
return 0;
eth_register(dev);
-#if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
miiphy_register(dev->name, npe_miiphy_read, npe_miiphy_write);
#endif