*/
#include <config.h>
-#include <version.h>
#include <asm/asm.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>
*/
#define MIPS_MAX_CACHE_SIZE 0x10000
-#define INDEX_BASE KSEG0
+#define INDEX_BASE CKSEG0
.macro cache_op op addr
.set push
*/
NESTED(mips_cache_reset, 0, ra)
move RA, ra
- li t2, CFG_ICACHE_SIZE
- li t3, CFG_DCACHE_SIZE
- li t4, CFG_CACHELINE_SIZE
+ li t2, CONFIG_SYS_ICACHE_SIZE
+ li t3, CONFIG_SYS_DCACHE_SIZE
+ li t4, CONFIG_SYS_CACHELINE_SIZE
move t5, t4
li v0, MIPS_MAX_CACHE_SIZE
/*
* Now clear that much memory starting from zero.
*/
- PTR_LI a0, KSEG1
+ PTR_LI a0, CKSEG1
PTR_ADDU a1, a0, v0
2: PTR_ADDIU a0, 64
f_fill64 a0, -64, zero
*/
move a1, t2
move a2, t4
- bal mips_init_icache
+ PTR_LA t7, mips_init_icache
+ jalr t7
/*
* then initialize D-cache.
*/
move a1, t3
move a2, t5
- bal mips_init_dcache
+ PTR_LA t7, mips_init_dcache
+ jalr t7
jr RA
END(mips_cache_reset)
and t0, t0, t1
ori t0, t0, CONF_CM_UNCACHED
mtc0 t0, CP0_CONFIG
- j ra
+ jr ra
END(dcache_disable)
-#ifdef CFG_INIT_RAM_LOCK_MIPS
+/*******************************************************************************
+*
+* dcache_enable - enable cache
+*
+* RETURNS: N/A
+*
+*/
+LEAF(dcache_enable)
+ mfc0 t0, CP0_CONFIG
+ ori t0, CONF_CM_CMASK
+ xori t0, CONF_CM_CMASK
+ ori t0, CONF_CM_CACHABLE_NONCOHERENT
+ mtc0 t0, CP0_CONFIG
+ jr ra
+ END(dcache_enable)
+
+#ifdef CONFIG_SYS_INIT_RAM_LOCK_MIPS
/*******************************************************************************
*
* mips_cache_lock - lock RAM area pointed to by a0 in cache.
*
*/
#if defined(CONFIG_PURPLE)
-# define CACHE_LOCK_SIZE (CFG_DCACHE_SIZE/2)
+# define CACHE_LOCK_SIZE (CONFIG_SYS_DCACHE_SIZE/2)
#else
-# define CACHE_LOCK_SIZE (CFG_DCACHE_SIZE)
+# define CACHE_LOCK_SIZE (CONFIG_SYS_DCACHE_SIZE)
#endif
.globl mips_cache_lock
.ent mips_cache_lock
mips_cache_lock:
- li a1, K0BASE - CACHE_LOCK_SIZE
+ li a1, CKSEG0 - CACHE_LOCK_SIZE
addu a0, a1
li a2, CACHE_LOCK_SIZE
- li a3, CFG_CACHELINE_SIZE
+ li a3, CONFIG_SYS_CACHELINE_SIZE
move a1, a2
icacheop(a0,a1,a2,a3,0x1d)
- j ra
+ jr ra
.end mips_cache_lock
-#endif /* CFG_INIT_RAM_LOCK_MIPS */
+#endif /* CONFIG_SYS_INIT_RAM_LOCK_MIPS */