rename CFG_ macros to CONFIG_SYS

[karo-tx-uboot.git] / cpu / mpc5xxx / pci_mpc5200.c

diff --git a/cpu/mpc5xxx/pci_mpc5200.c b/cpu/mpc5xxx/pci_mpc5200.c
index 94c157f6e882a6c000e9fc930e156886cfca8b85..a3251abf58d80a7eb715919c4aa00ede7f0bbf5f 100644 (file)
--- a/cpu/mpc5xxx/pci_mpc5200.c
+++ b/cpu/mpc5xxx/pci_mpc5200.c
@@ -31,8 +31,8 @@
 #include <mpc5xxx.h>
 
 /* System RAM mapped over PCI */
-#define CONFIG_PCI_MEMORY_BUS  CFG_SDRAM_BASE
-#define CONFIG_PCI_MEMORY_PHYS CFG_SDRAM_BASE
+#define CONFIG_PCI_MEMORY_BUS  CONFIG_SYS_SDRAM_BASE
+#define CONFIG_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE
 #define CONFIG_PCI_MEMORY_SIZE (1024 * 1024 * 1024)
 
 /* PCIIWCR bit fields */
@@ -49,7 +49,21 @@ static int mpc5200_read_config_dword(struct pci_controller *hose,
        *(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset;
        eieio();
        udelay(10);
+#if (defined CONFIG_PF5200 || defined CONFIG_CPCI5200)
+       if (dev & 0x00ff0000) {
+               u32 val;
+               val  = in_le16((volatile u16 *)(CONFIG_PCI_IO_PHYS+2));
+               udelay(10);
+               val = val << 16;
+               val |= in_le16((volatile u16 *)(CONFIG_PCI_IO_PHYS+0));
+               *value = val;
+       } else {
+               *value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS);
+       }
+       udelay(10);
+#else
        *value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS);
+#endif
        eieio();
        *(volatile u32 *)MPC5XXX_PCI_CAR = 0;
        udelay(10);
@@ -111,32 +125,27 @@ void pci_mpc5xxx_init (struct pci_controller *hose)
 
        /* Set cache line size */
        *(vu_long *)MPC5XXX_PCI_CFG = (*(vu_long *)MPC5XXX_PCI_CFG & ~0xff) |
-               (CFG_CACHELINE_SIZE / 4);
+               (CONFIG_SYS_CACHELINE_SIZE / 4);
 
        /* Map MBAR to PCI space */
-       *(vu_long *)MPC5XXX_PCI_BAR0 = CFG_MBAR;
-       *(vu_long *)MPC5XXX_PCI_TBATR0 = CFG_MBAR | 1;
+       *(vu_long *)MPC5XXX_PCI_BAR0 = CONFIG_SYS_MBAR;
+       *(vu_long *)MPC5XXX_PCI_TBATR0 = CONFIG_SYS_MBAR | 1;
 
        /* Map RAM to PCI space */
        *(vu_long *)MPC5XXX_PCI_BAR1 = CONFIG_PCI_MEMORY_BUS | (1 << 3);
        *(vu_long *)MPC5XXX_PCI_TBATR1 = CONFIG_PCI_MEMORY_PHYS | 1;
 
-       /* Enable snooping for RAM */
-       *(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (1 << 15);
-       *(vu_long *)(MPC5XXX_XLBARB + 0x70) = CONFIG_PCI_MEMORY_PHYS | 0x1d;
-
        /* Park XLB on PCI */
        *(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~((7 << 8) | (3 << 5));
        *(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (3 << 8) | (3 << 5);
 
-#if 0
-       /* Enable piplining */
-       *(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~(1 << 31);
-#endif
-
        /* Disable interrupts from PCI controller */
        *(vu_long *)MPC5XXX_PCI_GSCR &= ~(7 << 12);
-       *(vu_long *)MPC5XXX_PCI_ICR &= ~(7 << 24);
+       *(vu_long *)MPC5XXX_PCI_ICR  &= ~(7 << 24);
+
+       /* Set PCI retry counter to 0 = infinite retry. */
+       /* The default of 255 is too short for slow devices. */
+       *(vu_long *)MPC5XXX_PCI_ICR &= 0xFFFFFF00;
 
        /* Disable initiator windows */
        *(vu_long *)MPC5XXX_PCI_IWCR = 0;