ppc4xx: Dynamic configuration of 4xx PCIe mode as root or endpoint mode

[karo-tx-uboot.git] / cpu / ppc4xx / 4xx_pcie.c

diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c
index 7ee0e5bc89d14293170c41dbd79218f388f2b665..9ab358857ad590a761f8965e48eb9549528b84ac 100644 (file)
--- a/cpu/ppc4xx/4xx_pcie.c
+++ b/cpu/ppc4xx/4xx_pcie.c
@@ -46,6 +46,20 @@ enum {
        LNKW_X8                 = 0x8
 };
 
+static int validate_endpoint(struct pci_controller *hose)
+{
+       if (hose->cfg_data == (u8 *)CFG_PCIE0_CFGBASE)
+               return (is_end_point(0));
+       else if (hose->cfg_data == (u8 *)CFG_PCIE1_CFGBASE)
+               return (is_end_point(1));
+#if CFG_PCIE_NR_PORTS > 2
+       else if (hose->cfg_data == (u8 *)CFG_PCIE2_CFGBASE)
+               return (is_end_point(2));
+#endif
+
+       return 0;
+}
+
 static u8* pcie_get_base(struct pci_controller *hose, unsigned int devfn)
 {
        u8 *base = (u8*)hose->cfg_data;
@@ -95,6 +109,9 @@ static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
        u8 *address;
        *val = 0;
 
+       if (validate_endpoint(hose))
+               return 0;               /* No upstream config access */
+
        /*
         * Bus numbers are relative to hose->first_busno
         */
@@ -150,6 +167,9 @@ static int pcie_write_config(struct pci_controller *hose, unsigned int devfn,
 
        u8 *address;
 
+       if (validate_endpoint(hose))
+               return 0;               /* No upstream config access */
+
        /*
         * Bus numbers are relative to hose->first_busno
         */
@@ -595,9 +615,9 @@ int ppc4xx_init_pcie_port(int port, int rootport)
        u32 low, high;
 
        if (!core_init) {
-               ++core_init;
                if (ppc4xx_init_pcie())
                        return -1;
+               ++core_init;
        }
 
        /*