Status
------
U-Boot supports running as a coreboot [1] payload on x86. So far only Link
-(Chromebook Pixel) has been tested, but it should work with minimal adjustments
-on other x86 boards since coreboot deals with most of the low-level details.
+(Chromebook Pixel) and QEMU [2] x86 targets have been tested, but it should
+work with minimal adjustments on other x86 boards since coreboot deals with
+most of the low-level details.
U-Boot also supports booting directly from x86 reset vector without coreboot,
-aka raw support or bare support. Currently Link, Intel Crown Bay, Intel
-Minnowboard Max and Intel Galileo support running U-Boot 'bare metal'.
+aka raw support or bare support. Currently Link, QEMU x86 targets and all
+Intel boards support running U-Boot 'bare metal'.
As for loading an OS, U-Boot supports directly booting a 32-bit or 64-bit
Linux kernel as part of a FIT image. It also supports a compressed zImage.
$ make coreboot-x86_defconfig
$ make all
-Note this default configuration will build a U-Boot payload for the Link board.
+Note this default configuration will build a U-Boot payload for the QEMU board.
To build a coreboot payload against another board, you can change the build
configuration during the 'make menuconfig' process.
x86 architecture --->
...
- (chromebook_link) Board configuration file
- (chromebook_link) Board Device Tree Source (dts) file
- (0x19200000) Board specific Cache-As-RAM (CAR) address
+ (qemu-x86) Board configuration file
+ (qemu-x86_i440fx) Board Device Tree Source (dts) file
+ (0x01920000) Board specific Cache-As-RAM (CAR) address
(0x4000) Board specific Cache-As-RAM (CAR) size
Change the 'Board configuration file' and 'Board Device Tree Source (dts) file'
* ./mainboard/google/link/descriptor.bin
* ./mainboard/google/link/me.bin
-* ./northbridge/intel/sandybridge/systemagent-ivybridge.bin
+* ./northbridge/intel/sandybridge/systemagent-r6.bin
The 3rd one should be renamed to mrc.bin.
-As for the video ROM, you can get it here [2].
+As for the video ROM, you can get it here [3] and rename it to vga.bin.
Make sure all these binary blobs are put in the board directory.
Now you can build U-Boot and obtain u-boot.rom:
Intel Crown Bay specific instructions:
-U-Boot support of Intel Crown Bay board [3] relies on a binary blob called
-Firmware Support Package [4] to perform all the necessary initialization steps
+U-Boot support of Intel Crown Bay board [4] relies on a binary blob called
+Firmware Support Package [5] to perform all the necessary initialization steps
as documented in the BIOS Writer Guide, including initialization of the CPU,
memory controller, chipset and certain bus interfaces.
binary, change the following five bytes values from orginally E8 42 FF FF FF
to B8 00 80 0B 00.
+As for the video ROM, you need manually extract it from the Intel provided
+BIOS for Crown Bay here [6], using the AMI MMTool [7]. Check PCI option ROM
+ID 8086:4108, extract and save it as vga.bin in the board directory.
+
Now you can build U-Boot and obtain u-boot.rom
$ make crownbay_defconfig
$ make minnowmax_defconfig
$ make all
+Checksums are as follows (but note that newer versions will invalidate this):
+
+$ md5sum -b board/intel/minnowmax/*.bin
+ffda9a3b94df5b74323afb328d51e6b4 board/intel/minnowmax/descriptor.bin
+69f65b9a580246291d20d08cbef9d7c5 board/intel/minnowmax/fsp.bin
+894a97d371544ec21de9c3e8e1716c4b board/intel/minnowmax/me.bin
+a2588537da387da592a27219d56e9962 board/intel/minnowmax/vga.bin
+
+The ROM image is broken up into these parts:
+
+Offset Description Controlling config
+------------------------------------------------------------
+000000 descriptor.bin Hard-coded to 0 in ifdtool
+001000 me.bin Set by the descriptor
+500000 <spare>
+700000 u-boot-dtb.bin CONFIG_SYS_TEXT_BASE
+790000 vga.bin CONFIG_X86_OPTION_ROM_ADDR
+7c0000 fsp.bin CONFIG_FSP_ADDR
+7f8000 <spare> (depends on size of fsp.bin)
+7fe000 Environment CONFIG_ENV_OFFSET
+7ff800 U-Boot 16-bit boot CONFIG_SYS_X86_START16
+
+Overall ROM image size is controlled by CONFIG_ROM_SIZE.
+
+
Intel Galileo instructions:
Only one binary blob is needed for Remote Management Unit (RMU) within Intel
$ make galileo_defconfig
$ make all
+QEMU x86 target instructions:
+
+To build u-boot.rom for QEMU x86 targets, just simply run
+
+$ make qemu-x86_defconfig
+$ make all
+
+Note this default configuration will build a U-Boot for the QEMU x86 i440FX
+board. To build a U-Boot against QEMU x86 Q35 board, you can change the build
+configuration during the 'make menuconfig' process like below:
+
+Device Tree Control --->
+ ...
+ (qemu-x86_q35) Default Device Tree for DT control
+
Test with coreboot
------------------
For testing U-Boot as the coreboot payload, there are things that need be paid
the video information correctly (it always says the resolution is 0x0). This
works correctly for link though.
+Test with QEMU
+--------------
+QEMU is a fancy emulator that can enable us to test U-Boot without access to
+a real x86 board. Please make sure your QEMU version is 2.3.0 or above test
+U-Boot. To launch QEMU with u-boot.rom, call QEMU as follows:
+
+$ qemu-system-i386 -nographic -bios path/to/u-boot.rom
+
+This will instantiate an emulated x86 board with i440FX and PIIX chipset. QEMU
+also supports emulating an x86 board with Q35 and ICH9 based chipset, which is
+also supported by U-Boot. To instantiate such a machine, call QEMU with:
+
+$ qemu-system-i386 -nographic -bios path/to/u-boot.rom -M q35
+
+Note by default QEMU instantiated boards only have 128 MiB system memory. But
+it is enough to have U-Boot boot and function correctly. You can increase the
+system memory by pass '-m' parameter to QEMU if you want more memory:
+
+$ qemu-system-i386 -nographic -bios path/to/u-boot.rom -m 1024
+
+This creates a board with 1 GiB system memory. Currently U-Boot for QEMU only
+supports 3 GiB maximum system memory and reserves the last 1 GiB address space
+for PCI device memory-mapped I/O and other stuff, so the maximum value of '-m'
+would be 3072.
+
+QEMU emulates a graphic card which U-Boot supports. Removing '-nographic' will
+show QEMU's VGA console window. Note this will disable QEMU's serial output.
+If you want to check both consoles, use '-serial stdio'.
+
+Multicore is also supported by QEMU via '-smp n' where n is the number of cores
+to instantiate. Currently the default U-Boot built for QEMU supports 2 cores.
+In order to support more cores, you need add additional cpu nodes in the device
+tree and change CONFIG_MAX_CPUS accordingly.
CPU Microcode
-------------
-Modern CPUs usually require a special bit stream called microcode [5] to be
+Modern CPUs usually require a special bit stream called microcode [8] to be
loaded on the processor after power up in order to function properly. U-Boot
has already integrated these as hex dumps in the source tree.
+SMP Support
+-----------
+On a multicore system, U-Boot is executed on the bootstrap processor (BSP).
+Additional application processors (AP) can be brought up by U-Boot. In order to
+have an SMP kernel to discover all of the available processors, U-Boot needs to
+prepare configuration tables which contain the multi-CPUs information before
+loading the OS kernel. Currently U-Boot supports generating two types of tables
+for SMP, called Simple Firmware Interface (SFI) [9] and Multi-Processor (MP)
+[10] tables. The writing of these two tables are controlled by two Kconfig
+options GENERATE_SFI_TABLE and GENERATE_MP_TABLE.
+
Driver Model
------------
x86 has been converted to use driver model for serial and GPIO.
Useful Commands
---------------
-
In keeping with the U-Boot philosophy of providing functions to check and
adjust internal settings, there are several x86-specific commands that may be
useful:
References
----------
[1] http://www.coreboot.org
-[2] http://www.coreboot.org/~stepan/pci8086,0166.rom
-[3] http://www.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e660-eg20t-development-kit.html
-[4] http://www.intel.com/fsp
-[5] http://en.wikipedia.org/wiki/Microcode
+[2] http://www.qemu.org
+[3] http://www.coreboot.org/~stepan/pci8086,0166.rom
+[4] http://www.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e660-eg20t-development-kit.html
+[5] http://www.intel.com/fsp
+[6] http://www.intel.com/content/www/us/en/secure/intelligent-systems/privileged/e6xx-35-b1-cmc22211.html
+[7] http://www.ami.com/products/bios-uefi-tools-and-utilities/bios-uefi-utilities/
+[8] http://en.wikipedia.org/wiki/Microcode
+[9] http://simplefirmware.org
+[10] http://www.intel.com/design/archives/processors/pro/docs/242016.htm