Merge tag 'linux-kselftest-4.10-rc1-update' of git://git.kernel.org/pub/scm/linux...

[karo-tx-linux.git] / drivers / clk / qcom / clk-alpha-pll.c

diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 0cfbb2940e3e393dc81fbb1a4a881c135627ebac..47a1da3739ce98eb06dbd4939b0a218d63afe613 100644 (file)
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -18,6 +18,7 @@
 #include <linux/delay.h>
 
 #include "clk-alpha-pll.h"
+#include "common.h"
 
 #define PLL_MODE               0x00
 # define PLL_OUTCTRL           BIT(0)
@@ -49,6 +50,7 @@
 #define PLL_USER_CTL_U         0x14
 
 #define PLL_CONFIG_CTL         0x18
+#define PLL_CONFIG_CTL_U       0x20
 #define PLL_TEST_CTL           0x1c
 #define PLL_TEST_CTL_U         0x20
 #define PLL_STATUS             0x24
@@ -58,6 +60,7 @@
  */
 #define ALPHA_REG_BITWIDTH     40
 #define ALPHA_BITWIDTH         32
+#define ALPHA_16BIT_MASK       0xffff
 
 #define to_clk_alpha_pll(_hw) container_of(to_clk_regmap(_hw), \
                                           struct clk_alpha_pll, clkr)
@@ -106,6 +109,39 @@ static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse,
 #define wait_for_pll_offline(pll) \
        wait_for_pll(pll, PLL_OFFLINE_ACK, 0, "offline")
 
+void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
+                            const struct alpha_pll_config *config)
+{
+       u32 val, mask;
+       u32 off = pll->offset;
+
+       regmap_write(regmap, off + PLL_L_VAL, config->l);
+       regmap_write(regmap, off + PLL_ALPHA_VAL, config->alpha);
+       regmap_write(regmap, off + PLL_CONFIG_CTL, config->config_ctl_val);
+       regmap_write(regmap, off + PLL_CONFIG_CTL_U, config->config_ctl_hi_val);
+
+       val = config->main_output_mask;
+       val |= config->aux_output_mask;
+       val |= config->aux2_output_mask;
+       val |= config->early_output_mask;
+       val |= config->pre_div_val;
+       val |= config->post_div_val;
+       val |= config->vco_val;
+
+       mask = config->main_output_mask;
+       mask |= config->aux_output_mask;
+       mask |= config->aux2_output_mask;
+       mask |= config->early_output_mask;
+       mask |= config->pre_div_mask;
+       mask |= config->post_div_mask;
+       mask |= config->vco_mask;
+
+       regmap_update_bits(regmap, off + PLL_USER_CTL, mask, val);
+
+       if (pll->flags & SUPPORTS_FSM_MODE)
+               qcom_pll_set_fsm_mode(regmap, off + PLL_MODE, 6, 0);
+}
+
 static int clk_alpha_pll_hwfsm_enable(struct clk_hw *hw)
 {
        int ret;
@@ -163,6 +199,30 @@ static void clk_alpha_pll_hwfsm_disable(struct clk_hw *hw)
        wait_for_pll_disable(pll);
 }
 
+static int pll_is_enabled(struct clk_hw *hw, u32 mask)
+{
+       int ret;
+       u32 val, off;
+       struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+
+       off = pll->offset;
+       ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);
+       if (ret)
+               return ret;
+
+       return !!(val & mask);
+}
+
+static int clk_alpha_pll_hwfsm_is_enabled(struct clk_hw *hw)
+{
+       return pll_is_enabled(hw, PLL_ACTIVE_FLAG);
+}
+
+static int clk_alpha_pll_is_enabled(struct clk_hw *hw)
+{
+       return pll_is_enabled(hw, PLL_LOCK_DET);
+}
+
 static int clk_alpha_pll_enable(struct clk_hw *hw)
 {
        int ret;
@@ -303,9 +363,14 @@ clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
        regmap_read(pll->clkr.regmap, off + PLL_USER_CTL, &ctl);
        if (ctl & PLL_ALPHA_EN) {
                regmap_read(pll->clkr.regmap, off + PLL_ALPHA_VAL, &low);
-               regmap_read(pll->clkr.regmap, off + PLL_ALPHA_VAL_U, &high);
-               a = (u64)high << 32 | low;
-               a >>= ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH;
+               if (pll->flags & SUPPORTS_16BIT_ALPHA) {
+                       a = low & ALPHA_16BIT_MASK;
+               } else {
+                       regmap_read(pll->clkr.regmap, off + PLL_ALPHA_VAL_U,
+                                   &high);
+                       a = (u64)high << 32 | low;
+                       a >>= ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH;
+               }
        }
 
        return alpha_pll_calc_rate(prate, l, a);
@@ -326,11 +391,15 @@ static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
                return -EINVAL;
        }
 
-       a <<= (ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH);
-
        regmap_write(pll->clkr.regmap, off + PLL_L_VAL, l);
-       regmap_write(pll->clkr.regmap, off + PLL_ALPHA_VAL, a);
-       regmap_write(pll->clkr.regmap, off + PLL_ALPHA_VAL_U, a >> 32);
+
+       if (pll->flags & SUPPORTS_16BIT_ALPHA) {
+               regmap_write(pll->clkr.regmap, off + PLL_ALPHA_VAL,
+                            a & ALPHA_16BIT_MASK);
+       } else {
+               a <<= (ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH);
+               regmap_write(pll->clkr.regmap, off + PLL_ALPHA_VAL_U, a >> 32);
+       }
 
        regmap_update_bits(pll->clkr.regmap, off + PLL_USER_CTL,
                           PLL_VCO_MASK << PLL_VCO_SHIFT,
@@ -363,6 +432,7 @@ static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 const struct clk_ops clk_alpha_pll_ops = {
        .enable = clk_alpha_pll_enable,
        .disable = clk_alpha_pll_disable,
+       .is_enabled = clk_alpha_pll_is_enabled,
        .recalc_rate = clk_alpha_pll_recalc_rate,
        .round_rate = clk_alpha_pll_round_rate,
        .set_rate = clk_alpha_pll_set_rate,
@@ -372,6 +442,7 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_ops);
 const struct clk_ops clk_alpha_pll_hwfsm_ops = {
        .enable = clk_alpha_pll_hwfsm_enable,
        .disable = clk_alpha_pll_hwfsm_disable,
+       .is_enabled = clk_alpha_pll_hwfsm_is_enabled,
        .recalc_rate = clk_alpha_pll_recalc_rate,
        .round_rate = clk_alpha_pll_round_rate,
        .set_rate = clk_alpha_pll_set_rate,