Merge tag 'late-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

[karo-tx-linux.git] / drivers / clk / zynq / pll.c

diff --git a/drivers/clk/zynq/pll.c b/drivers/clk/zynq/pll.c
index 47e307c25a7b0703170be22449674677dce54eec..3226f54fa5956a357104f3f8675779179067b717 100644 (file)
--- a/drivers/clk/zynq/pll.c
+++ b/drivers/clk/zynq/pll.c
@@ -50,6 +50,9 @@ struct zynq_pll {
 #define PLLCTRL_RESET_MASK     1
 #define PLLCTRL_RESET_SHIFT    0
 
+#define PLL_FBDIV_MIN  13
+#define PLL_FBDIV_MAX  66
+
 /**
  * zynq_pll_round_rate() - Round a clock frequency
  * @hw:                Handle between common and hardware-specific interfaces
@@ -63,10 +66,10 @@ static long zynq_pll_round_rate(struct clk_hw *hw, unsigned long rate,
        u32 fbdiv;
 
        fbdiv = DIV_ROUND_CLOSEST(rate, *prate);
-       if (fbdiv < 13)
-               fbdiv = 13;
-       else if (fbdiv > 66)
-               fbdiv = 66;
+       if (fbdiv < PLL_FBDIV_MIN)
+               fbdiv = PLL_FBDIV_MIN;
+       else if (fbdiv > PLL_FBDIV_MAX)
+               fbdiv = PLL_FBDIV_MAX;
 
        return *prate * fbdiv;
 }
@@ -182,7 +185,13 @@ static const struct clk_ops zynq_pll_ops = {
 
 /**
  * clk_register_zynq_pll() - Register PLL with the clock framework
- * @np Pointer to the DT device node
+ * @name       PLL name
+ * @parent     Parent clock name
+ * @pll_ctrl   Pointer to PLL control register
+ * @pll_status Pointer to PLL status register
+ * @lock_index Bit index to this PLL's lock status bit in @pll_status
+ * @lock       Register lock
+ * Returns handle to the registered clock.
  */
 struct clk *clk_register_zynq_pll(const char *name, const char *parent,
                void __iomem *pll_ctrl, void __iomem *pll_status, u8 lock_index,