* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/kernel.h>
#include <crypto/algapi.h>
#include <crypto/des.h>
-//#define HIFN_DEBUG
-
-#ifdef HIFN_DEBUG
-#define dprintk(f, a...) printk(f, ##a)
-#else
-#define dprintk(f, a...) do {} while (0)
-#endif
-
static char hifn_pll_ref[sizeof("extNNN")] = "ext";
module_param_string(hifn_pll_ref, hifn_pll_ref, sizeof(hifn_pll_ref), 0444);
MODULE_PARM_DESC(hifn_pll_ref,
/* DMA registres */
-#define HIFN_DMA_CRA 0x0C /* DMA Command Ring Address */
-#define HIFN_DMA_SDRA 0x1C /* DMA Source Data Ring Address */
+#define HIFN_DMA_CRA 0x0C /* DMA Command Ring Address */
+#define HIFN_DMA_SDRA 0x1C /* DMA Source Data Ring Address */
#define HIFN_DMA_RRA 0x2C /* DMA Result Ring Address */
#define HIFN_DMA_DDRA 0x3C /* DMA Destination Data Ring Address */
#define HIFN_DMA_STCTL 0x40 /* DMA Status and Control */
-#define HIFN_DMA_INTREN 0x44 /* DMA Interrupt Enable */
+#define HIFN_DMA_INTREN 0x44 /* DMA Interrupt Enable */
#define HIFN_DMA_CFG1 0x48 /* DMA Configuration #1 */
#define HIFN_DMA_CFG2 0x6C /* DMA Configuration #2 */
#define HIFN_CHIP_ID 0x98 /* Chip ID */
#define HIFN_NAMESIZE 32
#define HIFN_MAX_RESULT_ORDER 5
-#define HIFN_D_CMD_RSIZE 24*1
-#define HIFN_D_SRC_RSIZE 80*1
-#define HIFN_D_DST_RSIZE 80*1
-#define HIFN_D_RES_RSIZE 24*1
+#define HIFN_D_CMD_RSIZE (24 * 1)
+#define HIFN_D_SRC_RSIZE (80 * 1)
+#define HIFN_D_DST_RSIZE (80 * 1)
+#define HIFN_D_RES_RSIZE (24 * 1)
#define HIFN_D_DST_DALIGN 4
#define HIFN_MAX_RESULT (8 + 4 + 4 + 20 + 4)
#define HIFN_USED_RESULT 12
-struct hifn_desc
-{
+struct hifn_desc {
volatile __le32 l;
volatile __le32 p;
};
struct hifn_dma {
- struct hifn_desc cmdr[HIFN_D_CMD_RSIZE+1];
- struct hifn_desc srcr[HIFN_D_SRC_RSIZE+1];
- struct hifn_desc dstr[HIFN_D_DST_RSIZE+1];
- struct hifn_desc resr[HIFN_D_RES_RSIZE+1];
+ struct hifn_desc cmdr[HIFN_D_CMD_RSIZE + 1];
+ struct hifn_desc srcr[HIFN_D_SRC_RSIZE + 1];
+ struct hifn_desc dstr[HIFN_D_DST_RSIZE + 1];
+ struct hifn_desc resr[HIFN_D_RES_RSIZE + 1];
u8 command_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_COMMAND];
u8 result_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_RESULT];
int cmdk, srck, dstk, resk;
};
-#define HIFN_FLAG_CMD_BUSY (1<<0)
-#define HIFN_FLAG_SRC_BUSY (1<<1)
-#define HIFN_FLAG_DST_BUSY (1<<2)
-#define HIFN_FLAG_RES_BUSY (1<<3)
-#define HIFN_FLAG_OLD_KEY (1<<4)
+#define HIFN_FLAG_CMD_BUSY (1 << 0)
+#define HIFN_FLAG_SRC_BUSY (1 << 1)
+#define HIFN_FLAG_DST_BUSY (1 << 2)
+#define HIFN_FLAG_RES_BUSY (1 << 3)
+#define HIFN_FLAG_OLD_KEY (1 << 4)
#define HIFN_DEFAULT_ACTIVE_NUM 5
-struct hifn_device
-{
+struct hifn_device {
char name[HIFN_NAMESIZE];
int irq;
u32 dmareg;
- void *sa[HIFN_D_RES_RSIZE];
+ void *sa[HIFN_D_RES_RSIZE];
spinlock_t lock;
struct tasklet_struct tasklet;
- struct crypto_queue queue;
+ struct crypto_queue queue;
struct list_head alg_list;
unsigned int pk_clk_freq;
#define HIFN_D_JUMP 0x40000000
#define HIFN_D_VALID 0x80000000
-struct hifn_base_command
-{
+struct hifn_base_command {
volatile __le16 masks;
volatile __le16 session_num;
volatile __le16 total_source_count;
/*
* Structure to help build up the command data structure.
*/
-struct hifn_crypt_command
-{
- volatile __le16 masks;
- volatile __le16 header_skip;
- volatile __le16 source_count;
- volatile __le16 reserved;
+struct hifn_crypt_command {
+ volatile __le16 masks;
+ volatile __le16 header_skip;
+ volatile __le16 source_count;
+ volatile __le16 reserved;
};
#define HIFN_CRYPT_CMD_ALG_MASK 0x0003 /* algorithm: */
/*
* Structure to help build up the command data structure.
*/
-struct hifn_mac_command
-{
- volatile __le16 masks;
- volatile __le16 header_skip;
- volatile __le16 source_count;
- volatile __le16 reserved;
+struct hifn_mac_command {
+ volatile __le16 masks;
+ volatile __le16 header_skip;
+ volatile __le16 source_count;
+ volatile __le16 reserved;
};
#define HIFN_MAC_CMD_ALG_MASK 0x0001
#define HIFN_MAC_CMD_POS_IPSEC 0x0200
#define HIFN_MAC_CMD_NEW_KEY 0x0800
-struct hifn_comp_command
-{
- volatile __le16 masks;
- volatile __le16 header_skip;
- volatile __le16 source_count;
- volatile __le16 reserved;
+struct hifn_comp_command {
+ volatile __le16 masks;
+ volatile __le16 header_skip;
+ volatile __le16 source_count;
+ volatile __le16 reserved;
};
#define HIFN_COMP_CMD_SRCLEN_M 0xc000
#define HIFN_COMP_CMD_ALG_MPPC 0x0001 /* MPPC */
#define HIFN_COMP_CMD_ALG_LZS 0x0000 /* LZS */
-struct hifn_base_result
-{
- volatile __le16 flags;
- volatile __le16 session;
- volatile __le16 src_cnt; /* 15:0 of source count */
- volatile __le16 dst_cnt; /* 15:0 of dest count */
+struct hifn_base_result {
+ volatile __le16 flags;
+ volatile __le16 session;
+ volatile __le16 src_cnt; /* 15:0 of source count */
+ volatile __le16 dst_cnt; /* 15:0 of dest count */
};
#define HIFN_BASE_RES_DSTOVERRUN 0x0200 /* destination overrun */
#define HIFN_BASE_RES_DSTLEN_M 0x3000 /* 17:16 of dest count */
#define HIFN_BASE_RES_DSTLEN_S 12
-struct hifn_comp_result
-{
+struct hifn_comp_result {
volatile __le16 flags;
volatile __le16 crc;
};
#define HIFN_COMP_RES_ENDMARKER 0x0002 /* LZS: end marker seen */
#define HIFN_COMP_RES_SRC_NOTZERO 0x0001 /* source expired */
-struct hifn_mac_result
-{
- volatile __le16 flags;
- volatile __le16 reserved;
+struct hifn_mac_result {
+ volatile __le16 flags;
+ volatile __le16 reserved;
/* followed by 0, 6, 8, or 10 u16's of the MAC, then crypt */
};
#define HIFN_MAC_RES_MISCOMPARE 0x0002 /* compare failed */
#define HIFN_MAC_RES_SRC_NOTZERO 0x0001 /* source expired */
-struct hifn_crypt_result
-{
+struct hifn_crypt_result {
volatile __le16 flags;
volatile __le16 reserved;
};
#define HIFN_POLL_SCALAR 0x0
#endif
-#define HIFN_MAX_SEGLEN 0xffff /* maximum dma segment len */
+#define HIFN_MAX_SEGLEN 0xffff /* maximum dma segment len */
#define HIFN_MAX_DMALEN 0x3ffff /* maximum dma length */
-struct hifn_crypto_alg
-{
+struct hifn_crypto_alg {
struct list_head entry;
struct crypto_alg alg;
struct hifn_device *dev;
#define ASYNC_SCATTERLIST_CACHE 16
-#define ASYNC_FLAGS_MISALIGNED (1<<0)
+#define ASYNC_FLAGS_MISALIGNED (1 << 0)
-struct hifn_cipher_walk
-{
+struct hifn_cipher_walk {
struct scatterlist cache[ASYNC_SCATTERLIST_CACHE];
u32 flags;
int num;
};
-struct hifn_context
-{
+struct hifn_context {
u8 key[HIFN_MAX_CRYPT_KEY_LENGTH];
struct hifn_device *dev;
unsigned int keysize;
};
-struct hifn_request_context
-{
+struct hifn_request_context {
u8 *iv;
unsigned int ivsize;
u8 op, type, mode, unused;
int i;
u32 ret;
- for (i=10000; i > 0; --i) {
+ for (i = 10000; i > 0; --i) {
ret = hifn_read_0(dev, HIFN_0_PUCTRL);
if (!(ret & HIFN_PUCTRL_RESET))
break;
}
if (!i)
- dprintk("%s: Failed to reset PUC unit.\n", dev->name);
+ dev_err(&dev->pdev->dev, "Failed to reset PUC unit.\n");
}
static void hifn_reset_puc(struct hifn_device *dev)
hifn_reset_puc(dev);
}
-static u32 hifn_next_signature(u_int32_t a, u_int cnt)
+static u32 hifn_next_signature(u32 a, u_int cnt)
{
int i;
u32 v;
for (i = 0; i < cnt; i++) {
-
/* get the parity */
v = a & 0x80080125;
v ^= v >> 16;
hifn_write_1(dev, HIFN_1_PUB_RESET, hifn_read_1(dev, HIFN_1_PUB_RESET) |
HIFN_PUBRST_RESET);
- for (i=100; i > 0; --i) {
+ for (i = 100; i > 0; --i) {
mdelay(1);
if ((hifn_read_1(dev, HIFN_1_PUB_RESET) & HIFN_PUBRST_RESET) == 0)
break;
}
- if (!i)
- dprintk("Chip %s: Failed to initialise public key engine.\n",
- dev->name);
- else {
+ if (!i) {
+ dev_err(&dev->pdev->dev, "Failed to initialise public key engine.\n");
+ } else {
hifn_write_1(dev, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE);
dev->dmareg |= HIFN_DMAIER_PUBDONE;
hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
- dprintk("Chip %s: Public key engine has been successfully "
- "initialised.\n", dev->name);
+ dev_dbg(&dev->pdev->dev, "Public key engine has been successfully initialised.\n");
}
- /*
- * Enable RNG engine.
- */
+ /* Enable RNG engine. */
hifn_write_1(dev, HIFN_1_RNG_CONFIG,
hifn_read_1(dev, HIFN_1_RNG_CONFIG) | HIFN_RNGCFG_ENA);
- dprintk("Chip %s: RNG engine has been successfully initialised.\n",
- dev->name);
+ dev_dbg(&dev->pdev->dev, "RNG engine has been successfully initialised.\n");
#ifdef CONFIG_CRYPTO_DEV_HIFN_795X_RNG
/* First value must be discarded */
}
}
- if (offtbl == NULL) {
- dprintk("Chip %s: Unknown card!\n", dev->name);
+ if (!offtbl) {
+ dev_err(&dev->pdev->dev, "Unknown card!\n");
return -ENODEV;
}
hifn_write_1(dev, HIFN_1_UNLOCK_SECRET2, 0);
mdelay(1);
- for (i=0; i<12; ++i) {
+ for (i = 0; i < 12; ++i) {
addr = hifn_next_signature(addr, offtbl[i] + 0x101);
hifn_write_1(dev, HIFN_1_UNLOCK_SECRET2, addr);
}
hifn_write_1(dev, HIFN_1_DMA_CNFG, dmacfg);
- dprintk("Chip %s: %s.\n", dev->name, pci_name(dev->pdev));
+ dev_dbg(&dev->pdev->dev, "%s %s.\n", dev->name, pci_name(dev->pdev));
return 0;
}
u32 dptr = dev->desc_dma;
int i;
- for (i=0; i<HIFN_D_CMD_RSIZE; ++i)
+ for (i = 0; i < HIFN_D_CMD_RSIZE; ++i)
dma->cmdr[i].p = __cpu_to_le32(dptr +
offsetof(struct hifn_dma, command_bufs[i][0]));
- for (i=0; i<HIFN_D_RES_RSIZE; ++i)
+ for (i = 0; i < HIFN_D_RES_RSIZE; ++i)
dma->resr[i].p = __cpu_to_le32(dptr +
offsetof(struct hifn_dma, result_bufs[i][0]));
- /*
- * Setup LAST descriptors.
- */
+ /* Setup LAST descriptors. */
dma->cmdr[HIFN_D_CMD_RSIZE].p = __cpu_to_le32(dptr +
offsetof(struct hifn_dma, cmdr[0]));
dma->srcr[HIFN_D_SRC_RSIZE].p = __cpu_to_le32(dptr +
* to calculate the optimal multiplier. For PCI we assume 66MHz, since that
* allows us to operate without the risk of overclocking the chip. If it
* actually uses 33MHz, the chip will operate at half the speed, this can be
- * overriden by specifying the frequency as module parameter (pci33).
+ * overridden by specifying the frequency as module parameter (pci33).
*
* Unfortunately the PCI clock is not very suitable since the HIFN needs a
* stable clock and the PCI clock frequency may vary, so the default is the
freq = simple_strtoul(hifn_pll_ref + 3, NULL, 10);
else {
freq = 66;
- printk(KERN_INFO "hifn795x: assuming %uMHz clock speed, "
- "override with hifn_pll_ref=%.3s<frequency>\n",
- freq, hifn_pll_ref);
+ dev_info(&dev->pdev->dev, "assuming %uMHz clock speed, override with hifn_pll_ref=%.3s<frequency>\n",
+ freq, hifn_pll_ref);
}
m = HIFN_PLL_FCK_MAX / freq;
mask = 0;
switch (rctx->op) {
- case ACRYPTO_OP_DECRYPT:
- mask = HIFN_BASE_CMD_CRYPT | HIFN_BASE_CMD_DECODE;
- break;
- case ACRYPTO_OP_ENCRYPT:
- mask = HIFN_BASE_CMD_CRYPT;
- break;
- case ACRYPTO_OP_HMAC:
- mask = HIFN_BASE_CMD_MAC;
- break;
- default:
- goto err_out;
+ case ACRYPTO_OP_DECRYPT:
+ mask = HIFN_BASE_CMD_CRYPT | HIFN_BASE_CMD_DECODE;
+ break;
+ case ACRYPTO_OP_ENCRYPT:
+ mask = HIFN_BASE_CMD_CRYPT;
+ break;
+ case ACRYPTO_OP_HMAC:
+ mask = HIFN_BASE_CMD_MAC;
+ break;
+ default:
+ goto err_out;
}
buf_pos += hifn_setup_base_command(dev, buf_pos, nbytes,
md |= HIFN_CRYPT_CMD_NEW_IV;
switch (rctx->mode) {
- case ACRYPTO_MODE_ECB:
- md |= HIFN_CRYPT_CMD_MODE_ECB;
- break;
- case ACRYPTO_MODE_CBC:
- md |= HIFN_CRYPT_CMD_MODE_CBC;
- break;
- case ACRYPTO_MODE_CFB:
- md |= HIFN_CRYPT_CMD_MODE_CFB;
- break;
- case ACRYPTO_MODE_OFB:
- md |= HIFN_CRYPT_CMD_MODE_OFB;
- break;
- default:
- goto err_out;
+ case ACRYPTO_MODE_ECB:
+ md |= HIFN_CRYPT_CMD_MODE_ECB;
+ break;
+ case ACRYPTO_MODE_CBC:
+ md |= HIFN_CRYPT_CMD_MODE_CBC;
+ break;
+ case ACRYPTO_MODE_CFB:
+ md |= HIFN_CRYPT_CMD_MODE_CFB;
+ break;
+ case ACRYPTO_MODE_OFB:
+ md |= HIFN_CRYPT_CMD_MODE_OFB;
+ break;
+ default:
+ goto err_out;
}
switch (rctx->type) {
- case ACRYPTO_TYPE_AES_128:
- if (ctx->keysize != 16)
- goto err_out;
- md |= HIFN_CRYPT_CMD_KSZ_128 |
- HIFN_CRYPT_CMD_ALG_AES;
- break;
- case ACRYPTO_TYPE_AES_192:
- if (ctx->keysize != 24)
- goto err_out;
- md |= HIFN_CRYPT_CMD_KSZ_192 |
- HIFN_CRYPT_CMD_ALG_AES;
- break;
- case ACRYPTO_TYPE_AES_256:
- if (ctx->keysize != 32)
- goto err_out;
- md |= HIFN_CRYPT_CMD_KSZ_256 |
- HIFN_CRYPT_CMD_ALG_AES;
- break;
- case ACRYPTO_TYPE_3DES:
- if (ctx->keysize != 24)
- goto err_out;
- md |= HIFN_CRYPT_CMD_ALG_3DES;
- break;
- case ACRYPTO_TYPE_DES:
- if (ctx->keysize != 8)
- goto err_out;
- md |= HIFN_CRYPT_CMD_ALG_DES;
- break;
- default:
+ case ACRYPTO_TYPE_AES_128:
+ if (ctx->keysize != 16)
+ goto err_out;
+ md |= HIFN_CRYPT_CMD_KSZ_128 |
+ HIFN_CRYPT_CMD_ALG_AES;
+ break;
+ case ACRYPTO_TYPE_AES_192:
+ if (ctx->keysize != 24)
goto err_out;
+ md |= HIFN_CRYPT_CMD_KSZ_192 |
+ HIFN_CRYPT_CMD_ALG_AES;
+ break;
+ case ACRYPTO_TYPE_AES_256:
+ if (ctx->keysize != 32)
+ goto err_out;
+ md |= HIFN_CRYPT_CMD_KSZ_256 |
+ HIFN_CRYPT_CMD_ALG_AES;
+ break;
+ case ACRYPTO_TYPE_3DES:
+ if (ctx->keysize != 24)
+ goto err_out;
+ md |= HIFN_CRYPT_CMD_ALG_3DES;
+ break;
+ case ACRYPTO_TYPE_DES:
+ if (ctx->keysize != 8)
+ goto err_out;
+ md |= HIFN_CRYPT_CMD_ALG_DES;
+ break;
+ default:
+ goto err_out;
}
buf_pos += hifn_setup_crypto_command(dev, buf_pos,
HIFN_D_VALID | HIFN_D_LAST |
HIFN_D_MASKDONEIRQ | HIFN_D_JUMP);
dma->cmdi = 0;
- } else
- dma->cmdr[dma->cmdi-1].l |= __cpu_to_le32(HIFN_D_VALID);
+ } else {
+ dma->cmdr[dma->cmdi - 1].l |= __cpu_to_le32(HIFN_D_VALID);
+ }
if (!(dev->flags & HIFN_FLAG_CMD_BUSY)) {
hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA);
sg_init_table(w->cache, num);
w->num = 0;
- for (i=0; i<num; ++i) {
+ for (i = 0; i < num; ++i) {
struct page *page = alloc_page(gfp_flags);
struct scatterlist *s;
{
int i;
- for (i=0; i<w->num; ++i) {
+ for (i = 0; i < w->num; ++i) {
struct scatterlist *s = &w->cache[i];
__free_page(sg_page(s));
drest -= copy;
nbytes -= copy;
- dprintk("%s: copy: %u, size: %u, drest: %u, nbytes: %u.\n",
- __func__, copy, size, drest, nbytes);
+ pr_debug("%s: copy: %u, size: %u, drest: %u, nbytes: %u.\n",
+ __func__, copy, size, drest, nbytes);
dst++;
idx++;
dst = &req->dst[idx];
- dprintk("\n%s: dlen: %u, doff: %u, offset: %u, nbytes: %u.\n",
- __func__, dst->length, dst->offset, offset, nbytes);
+ pr_debug("\n%s: dlen: %u, doff: %u, offset: %u, nbytes: %u.\n",
+ __func__, dst->length, dst->offset, offset, nbytes);
if (!IS_ALIGNED(dst->offset, HIFN_D_DST_DALIGN) ||
!IS_ALIGNED(dst->length, HIFN_D_DST_DALIGN) ||
* to put there additional blocksized chunk,
* so we mark that page as containing only
* blocksize aligned chunks:
- * t->length = (slen & ~(HIFN_D_DST_DALIGN - 1));
+ * t->length = (slen & ~(HIFN_D_DST_DALIGN - 1));
* and increase number of bytes to be processed
* in next chunk:
- * nbytes += diff;
+ * nbytes += diff;
*/
nbytes += diff;
* Temporary of course...
* Kick author if you will catch this one.
*/
- printk(KERN_ERR "%s: dlen: %u, nbytes: %u,"
- "slen: %u, offset: %u.\n",
- __func__, dlen, nbytes, slen, offset);
- printk(KERN_ERR "%s: please contact author to fix this "
- "issue, generally you should not catch "
- "this path under any condition but who "
- "knows how did you use crypto code.\n"
- "Thank you.\n", __func__);
+ pr_err("%s: dlen: %u, nbytes: %u, slen: %u, offset: %u.\n",
+ __func__, dlen, nbytes, slen, offset);
+ pr_err("%s: please contact author to fix this "
+ "issue, generally you should not catch "
+ "this path under any condition but who "
+ "knows how did you use crypto code.\n"
+ "Thank you.\n", __func__);
BUG();
} else {
copy += diff + nbytes;
spin_unlock_irqrestore(&dev->lock, flags);
err_out_exit:
if (err) {
- printk("%s: iv: %p [%d], key: %p [%d], mode: %u, op: %u, "
- "type: %u, err: %d.\n",
- dev->name, rctx->iv, rctx->ivsize,
- ctx->key, ctx->keysize,
- rctx->mode, rctx->op, rctx->type, err);
+ dev_info(&dev->pdev->dev, "iv: %p [%d], key: %p [%d], mode: %u, op: %u, "
+ "type: %u, err: %d.\n",
+ rctx->iv, rctx->ivsize,
+ ctx->key, ctx->keysize,
+ rctx->mode, rctx->op, rctx->type, err);
}
return err;
}
-static int hifn_test(struct hifn_device *dev, int encdec, u8 snum)
-{
- int n, err;
- u8 src[16];
- struct hifn_context ctx;
- struct hifn_request_context rctx;
- u8 fips_aes_ecb_from_zero[16] = {
- 0x66, 0xE9, 0x4B, 0xD4,
- 0xEF, 0x8A, 0x2C, 0x3B,
- 0x88, 0x4C, 0xFA, 0x59,
- 0xCA, 0x34, 0x2B, 0x2E};
- struct scatterlist sg;
-
- memset(src, 0, sizeof(src));
- memset(ctx.key, 0, sizeof(ctx.key));
-
- ctx.dev = dev;
- ctx.keysize = 16;
- rctx.ivsize = 0;
- rctx.iv = NULL;
- rctx.op = (encdec)?ACRYPTO_OP_ENCRYPT:ACRYPTO_OP_DECRYPT;
- rctx.mode = ACRYPTO_MODE_ECB;
- rctx.type = ACRYPTO_TYPE_AES_128;
- rctx.walk.cache[0].length = 0;
-
- sg_init_one(&sg, &src, sizeof(src));
-
- err = hifn_setup_dma(dev, &ctx, &rctx, &sg, &sg, sizeof(src), NULL);
- if (err)
- goto err_out;
-
- dev->started = 0;
- msleep(200);
-
- dprintk("%s: decoded: ", dev->name);
- for (n=0; n<sizeof(src); ++n)
- dprintk("%02x ", src[n]);
- dprintk("\n");
- dprintk("%s: FIPS : ", dev->name);
- for (n=0; n<sizeof(fips_aes_ecb_from_zero); ++n)
- dprintk("%02x ", fips_aes_ecb_from_zero[n]);
- dprintk("\n");
-
- if (!memcmp(src, fips_aes_ecb_from_zero, sizeof(fips_aes_ecb_from_zero))) {
- printk(KERN_INFO "%s: AES 128 ECB test has been successfully "
- "passed.\n", dev->name);
- return 0;
- }
-
-err_out:
- printk(KERN_INFO "%s: AES 128 ECB test has been failed.\n", dev->name);
- return -1;
-}
-
static int hifn_start_device(struct hifn_device *dev)
{
int err;
saddr += copy;
offset = 0;
- dprintk("%s: copy: %u, size: %u, srest: %u, nbytes: %u.\n",
- __func__, copy, size, srest, nbytes);
+ pr_debug("%s: copy: %u, size: %u, srest: %u, nbytes: %u.\n",
+ __func__, copy, size, srest, nbytes);
dst++;
idx++;
dev->sa[i] = NULL;
dev->started--;
if (dev->started < 0)
- printk("%s: started: %d.\n", __func__, dev->started);
+ dev_info(&dev->pdev->dev, "%s: started: %d.\n", __func__,
+ dev->started);
spin_unlock_irqrestore(&dev->lock, flags);
BUG_ON(dev->started < 0);
}
t = &rctx->walk.cache[idx];
dst = &req->dst[idx];
- dprintk("\n%s: sg_page(t): %p, t->length: %u, "
+ pr_debug("\n%s: sg_page(t): %p, t->length: %u, "
"sg_page(dst): %p, dst->length: %u, "
"nbytes: %u.\n",
__func__, sg_page(t), t->length,
struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
int i, u;
- dprintk("%s: ring cleanup 1: i: %d.%d.%d.%d, u: %d.%d.%d.%d, "
+ dev_dbg(&dev->pdev->dev, "ring cleanup 1: i: %d.%d.%d.%d, u: %d.%d.%d.%d, "
"k: %d.%d.%d.%d.\n",
- dev->name,
dma->cmdi, dma->srci, dma->dsti, dma->resi,
dma->cmdu, dma->srcu, dma->dstu, dma->resu,
dma->cmdk, dma->srck, dma->dstk, dma->resk);
}
dma->dstk = i; dma->dstu = u;
- dprintk("%s: ring cleanup 2: i: %d.%d.%d.%d, u: %d.%d.%d.%d, "
+ dev_dbg(&dev->pdev->dev, "ring cleanup 2: i: %d.%d.%d.%d, u: %d.%d.%d.%d, "
"k: %d.%d.%d.%d.\n",
- dev->name,
dma->cmdi, dma->srci, dma->dsti, dma->resi,
dma->cmdu, dma->srcu, dma->dstu, dma->resu,
dma->cmdk, dma->srck, dma->dstk, dma->resk);
int i;
struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
- printk("%s: r: %08x, active: %d, started: %d, "
- "success: %lu: qlen: %u/%u, reset: %d.\n",
- dev->name, r, dev->active, dev->started,
- dev->success, dev->queue.qlen, dev->queue.max_qlen,
- reset);
+ dev_info(&dev->pdev->dev,
+ "r: %08x, active: %d, started: %d, "
+ "success: %lu: qlen: %u/%u, reset: %d.\n",
+ r, dev->active, dev->started,
+ dev->success, dev->queue.qlen, dev->queue.max_qlen,
+ reset);
- printk("%s: res: ", __func__);
- for (i=0; i<HIFN_D_RES_RSIZE; ++i) {
- printk("%x.%p ", dma->resr[i].l, dev->sa[i]);
+ dev_info(&dev->pdev->dev, "%s: res: ", __func__);
+ for (i = 0; i < HIFN_D_RES_RSIZE; ++i) {
+ pr_info("%x.%p ", dma->resr[i].l, dev->sa[i]);
if (dev->sa[i]) {
hifn_process_ready(dev->sa[i], -ENODEV);
hifn_complete_sa(dev, i);
}
}
- printk("\n");
+ pr_info("\n");
hifn_reset_dma(dev, 1);
hifn_stop_device(dev);
dmacsr = hifn_read_1(dev, HIFN_1_DMA_CSR);
- dprintk("%s: 1 dmacsr: %08x, dmareg: %08x, res: %08x [%d], "
+ dev_dbg(&dev->pdev->dev, "1 dmacsr: %08x, dmareg: %08x, res: %08x [%d], "
"i: %d.%d.%d.%d, u: %d.%d.%d.%d.\n",
- dev->name, dmacsr, dev->dmareg, dmacsr & dev->dmareg, dma->cmdi,
+ dmacsr, dev->dmareg, dmacsr & dev->dmareg, dma->cmdi,
dma->cmdi, dma->srci, dma->dsti, dma->resi,
dma->cmdu, dma->srcu, dma->dstu, dma->resu);
if (restart) {
u32 puisr = hifn_read_0(dev, HIFN_0_PUISR);
- printk(KERN_WARNING "%s: overflow: r: %d, d: %d, puisr: %08x, d: %u.\n",
- dev->name, !!(dmacsr & HIFN_DMACSR_R_OVER),
- !!(dmacsr & HIFN_DMACSR_D_OVER),
+ dev_warn(&dev->pdev->dev, "overflow: r: %d, d: %d, puisr: %08x, d: %u.\n",
+ !!(dmacsr & HIFN_DMACSR_R_OVER),
+ !!(dmacsr & HIFN_DMACSR_D_OVER),
puisr, !!(puisr & HIFN_PUISR_DSTOVER));
if (!!(puisr & HIFN_PUISR_DSTOVER))
hifn_write_0(dev, HIFN_0_PUISR, HIFN_PUISR_DSTOVER);
restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT |
HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT);
if (restart) {
- printk(KERN_WARNING "%s: abort: c: %d, s: %d, d: %d, r: %d.\n",
- dev->name, !!(dmacsr & HIFN_DMACSR_C_ABORT),
- !!(dmacsr & HIFN_DMACSR_S_ABORT),
- !!(dmacsr & HIFN_DMACSR_D_ABORT),
- !!(dmacsr & HIFN_DMACSR_R_ABORT));
+ dev_warn(&dev->pdev->dev, "abort: c: %d, s: %d, d: %d, r: %d.\n",
+ !!(dmacsr & HIFN_DMACSR_C_ABORT),
+ !!(dmacsr & HIFN_DMACSR_S_ABORT),
+ !!(dmacsr & HIFN_DMACSR_D_ABORT),
+ !!(dmacsr & HIFN_DMACSR_R_ABORT));
hifn_reset_dma(dev, 1);
hifn_init_dma(dev);
hifn_init_registers(dev);
}
if ((dmacsr & HIFN_DMACSR_C_WAIT) && (dma->cmdu == 0)) {
- dprintk("%s: wait on command.\n", dev->name);
+ dev_dbg(&dev->pdev->dev, "wait on command.\n");
dev->dmareg &= ~(HIFN_DMAIER_C_WAIT);
hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
}
struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
int i;
- for (i=0; i<HIFN_D_RES_RSIZE; ++i) {
+ for (i = 0; i < HIFN_D_RES_RSIZE; ++i) {
struct hifn_desc *d = &dma->resr[i];
if (dev->sa[i]) {
hifn_process_ready(dev->sa[i],
- (d->l & __cpu_to_le32(HIFN_D_VALID))?-ENODEV:0);
+ (d->l & __cpu_to_le32(HIFN_D_VALID)) ? -ENODEV : 0);
hifn_complete_sa(dev, i);
}
}
spin_lock_irqsave(&dev->lock, flags);
while ((async_req = crypto_dequeue_request(&dev->queue))) {
- req = container_of(async_req, struct ablkcipher_request, base);
+ req = ablkcipher_request_cast(async_req);
spin_unlock_irqrestore(&dev->lock, flags);
hifn_process_ready(req, -ENODEV);
if (len == HIFN_DES_KEY_LENGTH) {
u32 tmp[DES_EXPKEY_WORDS];
int ret = des_ekey(tmp, key);
-
+
if (unlikely(ret == 0) && (tfm->crt_flags & CRYPTO_TFM_REQ_WEAK_KEY)) {
tfm->crt_flags |= CRYPTO_TFM_RES_WEAK_KEY;
return -EINVAL;
if (backlog)
backlog->complete(backlog, -EINPROGRESS);
- req = container_of(async_req, struct ablkcipher_request, base);
+ req = ablkcipher_request_cast(async_req);
err = hifn_handle_req(req);
if (err)
ACRYPTO_TYPE_3DES, ACRYPTO_MODE_OFB);
}
-/*
- * 3DES decryption functions.
- */
+/* 3DES decryption functions. */
static inline int hifn_decrypt_3des_ecb(struct ablkcipher_request *req)
{
return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
ACRYPTO_TYPE_3DES, ACRYPTO_MODE_OFB);
}
-struct hifn_alg_template
-{
+struct hifn_alg_template {
char name[CRYPTO_MAX_ALG_NAME];
char drv_name[CRYPTO_MAX_ALG_NAME];
unsigned int bsize;
struct hifn_crypto_alg *alg;
int err;
- alg = kzalloc(sizeof(struct hifn_crypto_alg), GFP_KERNEL);
+ alg = kzalloc(sizeof(*alg), GFP_KERNEL);
if (!alg)
return -ENOMEM;
{
int i, err;
- for (i=0; i<ARRAY_SIZE(hifn_alg_templates); ++i) {
+ for (i = 0; i < ARRAY_SIZE(hifn_alg_templates); ++i) {
err = hifn_alg_alloc(dev, &hifn_alg_templates[i]);
if (err)
goto err_out_exit;
goto err_out_disable_pci_device;
snprintf(name, sizeof(name), "hifn%d",
- atomic_inc_return(&hifn_dev_number)-1);
+ atomic_inc_return(&hifn_dev_number) - 1);
err = pci_request_regions(pdev, name);
if (err)
if (pci_resource_len(pdev, 0) < HIFN_BAR0_SIZE ||
pci_resource_len(pdev, 1) < HIFN_BAR1_SIZE ||
pci_resource_len(pdev, 2) < HIFN_BAR2_SIZE) {
- dprintk("%s: Broken hardware - I/O regions are too small.\n",
- pci_name(pdev));
+ dev_err(&pdev->dev, "Broken hardware - I/O regions are too small.\n");
err = -ENODEV;
goto err_out_free_regions;
}
snprintf(dev->name, sizeof(dev->name), "%s", name);
spin_lock_init(&dev->lock);
- for (i=0; i<3; ++i) {
+ for (i = 0; i < 3; ++i) {
unsigned long addr, size;
addr = pci_resource_start(pdev, i);
dev->desc_virt = pci_zalloc_consistent(pdev, sizeof(struct hifn_dma),
&dev->desc_dma);
if (!dev->desc_virt) {
- dprintk("Failed to allocate descriptor rings.\n");
+ dev_err(&pdev->dev, "Failed to allocate descriptor rings.\n");
err = -ENOMEM;
goto err_out_unmap_bars;
}
dev->pdev = pdev;
dev->irq = pdev->irq;
- for (i=0; i<HIFN_D_RES_RSIZE; ++i)
+ for (i = 0; i < HIFN_D_RES_RSIZE; ++i)
dev->sa[i] = NULL;
pci_set_drvdata(pdev, dev);
err = request_irq(dev->irq, hifn_interrupt, IRQF_SHARED, dev->name, dev);
if (err) {
- dprintk("Failed to request IRQ%d: err: %d.\n", dev->irq, err);
+ dev_err(&pdev->dev, "Failed to request IRQ%d: err: %d.\n",
+ dev->irq, err);
dev->irq = 0;
goto err_out_free_desc;
}
if (err)
goto err_out_free_irq;
- err = hifn_test(dev, 1, 0);
- if (err)
- goto err_out_stop_device;
-
err = hifn_register_rng(dev);
if (err)
goto err_out_stop_device;
INIT_DELAYED_WORK(&dev->work, hifn_work);
schedule_delayed_work(&dev->work, HZ);
- dprintk("HIFN crypto accelerator card at %s has been "
- "successfully registered as %s.\n",
- pci_name(pdev), dev->name);
+ dev_dbg(&pdev->dev, "HIFN crypto accelerator card at %s has been "
+ "successfully registered as %s.\n",
+ pci_name(pdev), dev->name);
return 0;
dev->desc_virt, dev->desc_dma);
err_out_unmap_bars:
- for (i=0; i<3; ++i)
+ for (i = 0; i < 3; ++i)
if (dev->bar[i])
iounmap(dev->bar[i]);
pci_free_consistent(pdev, sizeof(struct hifn_dma),
dev->desc_virt, dev->desc_dma);
- for (i=0; i<3; ++i)
+ for (i = 0; i < 3; ++i)
if (dev->bar[i])
iounmap(dev->bar[i]);
if (strncmp(hifn_pll_ref, "ext", 3) &&
strncmp(hifn_pll_ref, "pci", 3)) {
- printk(KERN_ERR "hifn795x: invalid hifn_pll_ref clock, "
- "must be pci or ext");
+ pr_err("hifn795x: invalid hifn_pll_ref clock, must be pci or ext");
return -EINVAL;
}
if (hifn_pll_ref[3] != '\0') {
freq = simple_strtoul(hifn_pll_ref + 3, NULL, 10);
if (freq < 20 || freq > 100) {
- printk(KERN_ERR "hifn795x: invalid hifn_pll_ref "
- "frequency, must be in the range "
- "of 20-100");
+ pr_err("hifn795x: invalid hifn_pll_ref frequency, must"
+ "be in the range of 20-100");
return -EINVAL;
}
}
err = pci_register_driver(&hifn_pci_driver);
if (err < 0) {
- dprintk("Failed to register PCI driver for %s device.\n",
- hifn_pci_driver.name);
+ pr_err("Failed to register PCI driver for %s device.\n",
+ hifn_pci_driver.name);
return -ENODEV;
}
- printk(KERN_INFO "Driver for HIFN 795x crypto accelerator chip "
- "has been successfully registered.\n");
+ pr_info("Driver for HIFN 795x crypto accelerator chip "
+ "has been successfully registered.\n");
return 0;
}
{
pci_unregister_driver(&hifn_pci_driver);
- printk(KERN_INFO "Driver for HIFN 795x crypto accelerator chip "
- "has been successfully unregistered.\n");
+ pr_info("Driver for HIFN 795x crypto accelerator chip "
+ "has been successfully unregistered.\n");
}
module_init(hifn_init);
projects / karo-tx-linux.git / blobdiff