return 0;
}
-static void set_sdr_ctrlcfg(struct socfpga_sdram_config *cfg)
+static u32 sdr_get_ctrlcfg(struct socfpga_sdram_config *cfg)
{
const u32 csbits =
((cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK) >>
u32 ctrl_cfg = cfg->ctrl_cfg;
- debug("\nConfiguring CTRLCFG\n");
-
/*
* SDRAM Failure When Accessing Non-Existent Memory
* Set the addrorder field of the SDRAM control register
ctrl_cfg &= ~SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK;
ctrl_cfg |= addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
- writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
+ return ctrl_cfg;
}
-static void set_sdr_addr_rw(struct socfpga_sdram_config *cfg)
+static u32 sdr_get_addr_rw(struct socfpga_sdram_config *cfg)
{
/*
* SDRAM Failure When Accessing Non-Existent Memory
const int rows = get_errata_rows(cfg);
u32 dram_addrw = cfg->dram_addrw & ~SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK;
- debug("Configuring DRAMADDRW\n");
- writel(dram_addrw | (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB),
- &sdr_ctrl->dram_addrw);
+ return dram_addrw | (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB);
}
-/* Function to initialize SDRAM MMR */
-unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg)
+/**
+ * sdr_load_regs() - Load SDRAM controller registers
+ * @cfg: SDRAM controller configuration data
+ *
+ * This function loads the register values into the SDRAM controller block.
+ */
+static void sdr_load_regs(struct socfpga_sdram_config *cfg)
{
- unsigned long status = 0;
- struct socfpga_sdram_config *cfg = &sdram_config;
- const unsigned int rows =
- (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
- SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
-
- writel(rows, &sysmgr_regs->iswgrp_handoff[4]);
+ const u32 ctrl_cfg = sdr_get_ctrlcfg(cfg);
+ const u32 dram_addrw = sdr_get_addr_rw(cfg);
- set_sdr_ctrlcfg(cfg);
+ debug("\nConfiguring CTRLCFG\n");
+ writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
debug("Configuring DRAMTIMING1\n");
writel(cfg->dram_timing1, &sdr_ctrl->dram_timing1);
debug("Configuring LOWPWRTIMING\n");
writel(cfg->lowpwr_timing, &sdr_ctrl->lowpwr_timing);
- set_sdr_addr_rw(cfg);
+ debug("Configuring DRAMADDRW\n");
+ writel(dram_addrw, &sdr_ctrl->dram_addrw);
debug("Configuring DRAMIFWIDTH\n");
writel(cfg->dram_if_width, &sdr_ctrl->dram_if_width);
debug("Configuring DRAMODT\n");
writel(cfg->dram_odt, &sdr_ctrl->dram_odt);
+}
+
+/* Function to initialize SDRAM MMR */
+unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg)
+{
+ unsigned long status = 0;
+ struct socfpga_sdram_config *cfg = &sdram_config;
+ const unsigned int rows =
+ (cfg->dram_addrw & SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK) >>
+ SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB;
+
+ writel(rows, &sysmgr_regs->iswgrp_handoff[4]);
+
+ sdr_load_regs(cfg);
/* saving this value to SYSMGR.ISWGRP.HANDOFF.FPGA2SDR */
writel(cfg->fpgaport_rst, &sysmgr_regs->iswgrp_handoff[3]);