*/
#include "../../../board/altera/socfpga/qts/sdram_config.h"
-/* define constant for 4G memory - used for SDRAM errata workaround */
-#define MEMSIZE_4G (4ULL * 1024ULL * 1024ULL * 1024ULL)
-
DECLARE_GLOBAL_DATA_PTR;
struct sdram_prot_rule {
static struct socfpga_system_manager *sysmgr_regs =
(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
static struct socfpga_sdr_ctrl *sdr_ctrl =
- (struct socfpga_sdr_ctrl *)(SOCFPGA_SDR_ADDRESS + SDR_CTRLGRP_ADDRESS);
+ (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
-static int compute_errata_rows(unsigned long long memsize, int cs, int width,
- int rows, int banks, int cols)
+/**
+ * get_errata_rows() - Up the number of DRAM rows to cover entire address space
+ *
+ * SDRAM Failure happens when accessing non-existent memory. Artificially
+ * increase the number of rows so that the memory controller thinks it has
+ * 4GB of RAM. This function returns such amount of rows.
+ */
+static int get_errata_rows(void)
{
+ /* Define constant for 4G memory - used for SDRAM errata workaround */
+#define MEMSIZE_4G (4ULL * 1024ULL * 1024ULL * 1024ULL)
+ const unsigned long long memsize = MEMSIZE_4G;
+ const unsigned int cs = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS;
+ const unsigned int rows = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS;
+ const unsigned int banks = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS;
+ const unsigned int cols = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS;
+ const unsigned int width = 8;
+
unsigned long long newrows;
- int inewrowslog2;
- int bits;
+ int bits, inewrowslog2;
debug("workaround rows - memsize %lld\n", memsize);
debug("workaround rows - cs %d\n", cs);
debug("workaround rows - banks %d\n", banks);
debug("workaround rows - cols %d\n", cols);
- newrows = lldiv(memsize, (cs * (width / 8)));
+ newrows = lldiv(memsize, cs * (width / 8));
debug("rows workaround - term1 %lld\n", newrows);
- newrows = lldiv(newrows, ((1 << banks) * (1 << cols)));
+ newrows = lldiv(newrows, (1 << banks) * (1 << cols));
debug("rows workaround - term2 %lld\n", newrows);
- /* Compute the hamming weight - same as number of bits set.
+ /*
+ * Compute the hamming weight - same as number of bits set.
* Need to see if result is ordinal power of 2 before
* attempting log2 of result.
*/
- bits = hweight32(newrows);
+ bits = generic_hweight32(newrows);
debug("rows workaround - bits %d\n", bits);
return rows;
}
- inewrowslog2 = __ilog2((unsigned int)newrows);
+ inewrowslog2 = __ilog2(newrows);
- debug("rows workaround - ilog2 %d, %d\n", inewrowslog2,
- (int)newrows);
+ debug("rows workaround - ilog2 %d, %lld\n", inewrowslog2, newrows);
if (inewrowslog2 == -1) {
- printf("SDRAM workaround failed, newrows %d\n", (int)newrows);
+ printf("SDRAM workaround failed, newrows %lld\n", newrows);
return rows;
}
static void set_sdr_ctrlcfg(void)
{
- int addrorder;
+ u32 addrorder;
+ u32 ctrl_cfg =
+ (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
+ SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
+ SDR_CTRLGRP_CTRLCFG_MEMBL_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
+ SDR_CTRLGRP_CTRLCFG_ECCEN_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
+ SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
+ SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
+ SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
+ SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
+ SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB);
debug("\nConfiguring CTRLCFG\n");
- clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK,
- CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
- SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB);
- clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_MEMBL_MASK,
- CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
- SDR_CTRLGRP_CTRLCFG_MEMBL_LSB);
-
- /* SDRAM Failure When Accessing Non-Existent Memory
+ /*
+ * SDRAM Failure When Accessing Non-Existent Memory
* Set the addrorder field of the SDRAM control register
* based on the CSBITs setting.
*/
case 1:
addrorder = 0; /* chip, row, bank, column */
if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER != 0)
- debug("INFO: Changing address order to 0 (chip, row, \
- bank, column)\n");
+ debug("INFO: Changing address order to 0 (chip, row, bank, column)\n");
break;
case 2:
addrorder = 2; /* row, chip, bank, column */
if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER != 2)
- debug("INFO: Changing address order to 2 (row, chip, \
- bank, column)\n");
+ debug("INFO: Changing address order to 2 (row, chip, bank, column)\n");
break;
default:
addrorder = CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER;
break;
}
- clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK,
- addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB);
+ ctrl_cfg |= addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
- clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_ECCEN_MASK,
- CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
- SDR_CTRLGRP_CTRLCFG_ECCEN_LSB);
-
- clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK,
- CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
- SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB);
-
- clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK,
- CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
- SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB);
-
- clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK,
- CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
- SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB);
-
- clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK,
- CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
- SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB);
-
- clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK,
- CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
- SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB);
+ writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
}
-static void set_sdr_dram_timing1(void)
+static void set_sdr_dram_timing(void)
{
- debug("Configuring DRAMTIMING1\n");
- clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK,
- CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<
- SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB);
+ const u32 dram_timing1 =
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL <<
+ SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<
+ SDR_CTRLGRP_DRAMTIMING1_TAL_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<
+ SDR_CTRLGRP_DRAMTIMING1_TCL_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<
+ SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<
+ SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<
+ SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB);
- clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TAL_MASK,
- CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL <<
- SDR_CTRLGRP_DRAMTIMING1_TAL_LSB);
+ const u32 dram_timing2 =
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<
+ SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD <<
+ SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<
+ SDR_CTRLGRP_DRAMTIMING2_TRP_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<
+ SDR_CTRLGRP_DRAMTIMING2_TWR_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<
+ SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB);
- clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TCL_MASK,
- CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL <<
- SDR_CTRLGRP_DRAMTIMING1_TCL_LSB);
+ const u32 dram_timing3 =
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<
+ SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<
+ SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC <<
+ SDR_CTRLGRP_DRAMTIMING3_TRC_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<
+ SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<
+ SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB);
- clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK,
- CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD <<
- SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB);
+ const u32 dram_timing4 =
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<
+ SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<
+ SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB);
- clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK,
- CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW <<
- SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB);
+ const u32 lowpwr_timing =
+ (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<
+ SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<
+ SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB);
- clrsetbits_le32(&sdr_ctrl->dram_timing1, SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK,
- CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC <<
- SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB);
-}
+ debug("Configuring DRAMTIMING1\n");
+ writel(dram_timing1, &sdr_ctrl->dram_timing1);
-static void set_sdr_dram_timing2(void)
-{
debug("Configuring DRAMTIMING2\n");
- clrsetbits_le32(&sdr_ctrl->dram_timing2, SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK,
- CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI <<
- SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB);
-
- clrsetbits_le32(&sdr_ctrl->dram_timing2, SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK,
- CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD <<
- SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB);
-
- clrsetbits_le32(&sdr_ctrl->dram_timing2, SDR_CTRLGRP_DRAMTIMING2_TRP_MASK,
- CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP <<
- SDR_CTRLGRP_DRAMTIMING2_TRP_LSB);
-
- clrsetbits_le32(&sdr_ctrl->dram_timing2, SDR_CTRLGRP_DRAMTIMING2_TWR_MASK,
- CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR <<
- SDR_CTRLGRP_DRAMTIMING2_TWR_LSB);
-
- clrsetbits_le32(&sdr_ctrl->dram_timing2, SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK,
- CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR <<
- SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB);
-}
+ writel(dram_timing2, &sdr_ctrl->dram_timing2);
-static void set_sdr_dram_timing3(void)
-{
debug("Configuring DRAMTIMING3\n");
- clrsetbits_le32(&sdr_ctrl->dram_timing3, SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK,
- CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP <<
- SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB);
-
- clrsetbits_le32(&sdr_ctrl->dram_timing3, SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK,
- CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS <<
- SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB);
-
- clrsetbits_le32(&sdr_ctrl->dram_timing3, SDR_CTRLGRP_DRAMTIMING3_TRC_MASK,
- CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC <<
- SDR_CTRLGRP_DRAMTIMING3_TRC_LSB);
+ writel(dram_timing3, &sdr_ctrl->dram_timing3);
- clrsetbits_le32(&sdr_ctrl->dram_timing3, SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK,
- CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD <<
- SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB);
-
- clrsetbits_le32(&sdr_ctrl->dram_timing3, SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK,
- CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD <<
- SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB);
-}
-
-static void set_sdr_dram_timing4(void)
-{
debug("Configuring DRAMTIMING4\n");
- clrsetbits_le32(&sdr_ctrl->dram_timing4,
- SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK,
- CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT <<
- SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB);
-
- clrsetbits_le32(&sdr_ctrl->dram_timing4,
- SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK,
- CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT <<
- SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB);
-}
+ writel(dram_timing4, &sdr_ctrl->dram_timing4);
-static void set_sdr_dram_lowpwr_timing(void)
-{
debug("Configuring LOWPWRTIMING\n");
- clrsetbits_le32(&sdr_ctrl->lowpwr_timing,
- SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK,
- CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES <<
- SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB);
-
- clrsetbits_le32(&sdr_ctrl->lowpwr_timing,
- SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK,
- CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES <<
- SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB);
+ writel(lowpwr_timing, &sdr_ctrl->lowpwr_timing);
}
static void set_sdr_addr_rw(void)
{
- int cs = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS;
- int width = 8;
- int rows = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS;
- int banks = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS;
- int cols = CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS;
- unsigned long long workaround_memsize = MEMSIZE_4G;
-
- debug("Configuring DRAMADDRW\n");
- clrsetbits_le32(&sdr_ctrl->dram_addrw, SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK,
- CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
- SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB);
/*
* SDRAM Failure When Accessing Non-Existent Memory
- * Update Preloader to artificially increase the number of rows so
- * that the memory thinks it has 4GB of RAM.
- */
- rows = compute_errata_rows(workaround_memsize, cs, width, rows, banks,
- cols);
-
- clrsetbits_le32(&sdr_ctrl->dram_addrw, SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK,
- rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB);
-
- clrsetbits_le32(&sdr_ctrl->dram_addrw, SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK,
- CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
- SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB);
- /* SDRAM Failure When Accessing Non-Existent Memory
* Set SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB to
* log2(number of chip select bits). Since there's only
* 1 or 2 chip selects, log2(1) => 0, and log2(2) => 1,
* which is the same as "chip selects" - 1.
*/
- clrsetbits_le32(&sdr_ctrl->dram_addrw, SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK,
- (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
+ const int rows = get_errata_rows();
+ const u32 dram_addrw =
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS <<
+ SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB) |
+ (rows << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS <<
+ SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB) |
+ ((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) <<
SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB);
+ debug("Configuring DRAMADDRW\n");
+ writel(dram_addrw, &sdr_ctrl->dram_addrw);
}
static void set_sdr_static_cfg(void)
{
- debug("Configuring STATICCFG\n");
- clrsetbits_le32(&sdr_ctrl->static_cfg, SDR_CTRLGRP_STATICCFG_MEMBL_MASK,
- CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<
- SDR_CTRLGRP_STATICCFG_MEMBL_LSB);
-
- clrsetbits_le32(&sdr_ctrl->static_cfg,
- SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK,
- CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<
+ const u32 static_cfg =
+ (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL <<
+ SDR_CTRLGRP_STATICCFG_MEMBL_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA <<
SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB);
+
+ debug("Configuring STATICCFG\n");
+ writel(static_cfg, &sdr_ctrl->static_cfg);
}
static void set_sdr_fifo_cfg(void)
{
- debug("Configuring FIFOCFG\n");
- clrsetbits_le32(&sdr_ctrl->fifo_cfg, SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK,
- CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<
- SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB);
-
- clrsetbits_le32(&sdr_ctrl->fifo_cfg, SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK,
- CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC <<
+ const u32 fifo_cfg =
+ (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE <<
+ SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC <<
SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB);
+
+ debug("Configuring FIFOCFG\n");
+ writel(fifo_cfg, &sdr_ctrl->fifo_cfg);
}
static void set_sdr_mp_weight(void)
{
- debug("Configuring MPWEIGHT_MPWEIGHT_0\n");
- clrsetbits_le32(&sdr_ctrl->mp_weight0,
- SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK,
- CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
+ const u32 mp_weight0 =
+ (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB);
-
- clrsetbits_le32(&sdr_ctrl->mp_weight1,
- SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK,
- CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
- SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB);
-
- clrsetbits_le32(&sdr_ctrl->mp_weight1,
- SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK,
- CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
+ const u32 mp_weight1 =
+ (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
+ SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB);
-
- clrsetbits_le32(&sdr_ctrl->mp_weight2,
- SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK,
- CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
+ const u32 mp_weight2 =
+ (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB);
-
- clrsetbits_le32(&sdr_ctrl->mp_weight3,
- SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK,
- CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
+ const u32 mp_weight3 =
+ (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB);
+
+ debug("Configuring MPWEIGHT_MPWEIGHT_0\n");
+ writel(mp_weight0, &sdr_ctrl->mp_weight0);
+ writel(mp_weight1, &sdr_ctrl->mp_weight1);
+ writel(mp_weight2, &sdr_ctrl->mp_weight2);
+ writel(mp_weight3, &sdr_ctrl->mp_weight3);
}
static void set_sdr_mp_pacing(void)
{
- debug("Configuring MPPACING_MPPACING_0\n");
- clrsetbits_le32(&sdr_ctrl->mp_pacing0,
- SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK,
- CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
+ const u32 mp_pacing0 =
+ (CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB);
-
- clrsetbits_le32(&sdr_ctrl->mp_pacing1,
- SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK,
- CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
- SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB);
-
- clrsetbits_le32(&sdr_ctrl->mp_pacing1,
- SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK,
- CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
+ const u32 mp_pacing1 =
+ (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
+ SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB) |
+ (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB);
-
- clrsetbits_le32(&sdr_ctrl->mp_pacing2,
- SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK,
- CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
+ const u32 mp_pacing2 =
+ (CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB);
-
- clrsetbits_le32(&sdr_ctrl->mp_pacing3,
- SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK,
- CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
+ const u32 mp_pacing3 =
+ (CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB);
+
+ debug("Configuring MPPACING_MPPACING_0\n");
+ writel(mp_pacing0, &sdr_ctrl->mp_pacing0);
+ writel(mp_pacing1, &sdr_ctrl->mp_pacing1);
+ writel(mp_pacing2, &sdr_ctrl->mp_pacing2);
+ writel(mp_pacing3, &sdr_ctrl->mp_pacing3);
}
static void set_sdr_mp_threshold(void)
{
- debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n");
- clrsetbits_le32(&sdr_ctrl->mp_threshold0,
- SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK,
- CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
+ const u32 mp_threshold0 =
+ (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB);
-
- clrsetbits_le32(&sdr_ctrl->mp_threshold1,
- SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK,
- SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK <<
+ const u32 mp_threshold1 =
+ (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB);
-
- clrsetbits_le32(&sdr_ctrl->mp_threshold2,
- SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK,
- CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
+ const u32 mp_threshold2 =
+ (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB);
-}
+ debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n");
+ writel(mp_threshold0, &sdr_ctrl->mp_threshold0);
+ writel(mp_threshold1, &sdr_ctrl->mp_threshold1);
+ writel(mp_threshold2, &sdr_ctrl->mp_threshold2);
+}
/* Function to initialize SDRAM MMR */
unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg)
&sysmgr_regs->iswgrp_handoff[4]);
#endif
set_sdr_ctrlcfg();
- set_sdr_dram_timing1();
- set_sdr_dram_timing2();
- set_sdr_dram_timing3();
- set_sdr_dram_timing4();
- set_sdr_dram_lowpwr_timing();
+ set_sdr_dram_timing();
set_sdr_addr_rw();
debug("Configuring DRAMIFWIDTH\n");
projects / karo-tx-uboot.git / blobdiff