ddr: altera: sdram: Clean up set_sdr_mp_threshold()

[karo-tx-uboot.git] / drivers / ddr / altera / sdram.c

diff --git a/drivers/ddr/altera/sdram.c b/drivers/ddr/altera/sdram.c
index 8db8dde5dd90abeae835427d26096ed51db626b2..58fe26ef4aa4ecb0b2841d8fc0fc4b7c127030e1 100644 (file)
--- a/drivers/ddr/altera/sdram.c
+++ b/drivers/ddr/altera/sdram.c
@@ -417,81 +417,69 @@ static void set_sdr_fifo_cfg(void)
 
 static void set_sdr_mp_weight(void)
 {
-       debug("Configuring MPWEIGHT_MPWEIGHT_0\n");
-       clrsetbits_le32(&sdr_ctrl->mp_weight0,
-                       SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK,
-                       CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
+       const u32 mp_weight0 =
+               (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 <<
                        SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB);
-
-       clrsetbits_le32(&sdr_ctrl->mp_weight1,
-                       SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK,
-                       CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
-                       SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB);
-
-       clrsetbits_le32(&sdr_ctrl->mp_weight1,
-                       SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK,
-                       CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
+       const u32 mp_weight1 =
+               (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 <<
+                       SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB) |
+               (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 <<
                        SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB);
-
-       clrsetbits_le32(&sdr_ctrl->mp_weight2,
-                       SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK,
-                       CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
+       const u32 mp_weight2 =
+               (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 <<
                        SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB);
-
-       clrsetbits_le32(&sdr_ctrl->mp_weight3,
-                       SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK,
-                       CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
+       const u32 mp_weight3 =
+               (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 <<
                        SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB);
+
+       debug("Configuring MPWEIGHT_MPWEIGHT_0\n");
+       writel(mp_weight0, &sdr_ctrl->mp_weight0);
+       writel(mp_weight1, &sdr_ctrl->mp_weight1);
+       writel(mp_weight2, &sdr_ctrl->mp_weight2);
+       writel(mp_weight3, &sdr_ctrl->mp_weight3);
 }
 
 static void set_sdr_mp_pacing(void)
 {
-       debug("Configuring MPPACING_MPPACING_0\n");
-       clrsetbits_le32(&sdr_ctrl->mp_pacing0,
-                       SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK,
-                       CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
+       const u32 mp_pacing0 =
+               (CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 <<
                        SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB);
-
-       clrsetbits_le32(&sdr_ctrl->mp_pacing1,
-                       SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK,
-                       CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
-                       SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB);
-
-       clrsetbits_le32(&sdr_ctrl->mp_pacing1,
-                       SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK,
-                       CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
+       const u32 mp_pacing1 =
+               (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 <<
+                       SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB) |
+               (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 <<
                        SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB);
-
-       clrsetbits_le32(&sdr_ctrl->mp_pacing2,
-                       SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK,
-                       CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
+       const u32 mp_pacing2 =
+               (CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 <<
                        SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB);
-
-       clrsetbits_le32(&sdr_ctrl->mp_pacing3,
-                       SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK,
-                       CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
+       const u32 mp_pacing3 =
+               (CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 <<
                        SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB);
+
+       debug("Configuring MPPACING_MPPACING_0\n");
+       writel(mp_pacing0, &sdr_ctrl->mp_pacing0);
+       writel(mp_pacing1, &sdr_ctrl->mp_pacing1);
+       writel(mp_pacing2, &sdr_ctrl->mp_pacing2);
+       writel(mp_pacing3, &sdr_ctrl->mp_pacing3);
 }
 
 static void set_sdr_mp_threshold(void)
 {
-       debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n");
-       clrsetbits_le32(&sdr_ctrl->mp_threshold0,
-                       SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK,
-                       CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
+       const u32 mp_threshold0 =
+               (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 <<
                        SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB);
-
-       clrsetbits_le32(&sdr_ctrl->mp_threshold1,
-                       SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK,
-                       CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
+       const u32 mp_threshold1 =
+               (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 <<
                        SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB);
-
-       clrsetbits_le32(&sdr_ctrl->mp_threshold2,
-                       SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK,
-                       CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
+       const u32 mp_threshold2 =
+               (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 <<
                        SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB);
-}
 
+       debug("Configuring MPTHRESHOLDRST_MPTHRESHOLDRST_0\n");
+       writel(mp_threshold0, &sdr_ctrl->mp_threshold0);
+       writel(mp_threshold1, &sdr_ctrl->mp_threshold1);
+       writel(mp_threshold2, &sdr_ctrl->mp_threshold2);
+}
 
 /* Function to initialize SDRAM MMR */
 unsigned sdram_mmr_init_full(unsigned int sdr_phy_reg)