*/
}
-/*
- * issue write test command.
- * two variants are provided. one that just tests a write pattern and
- * another that tests datamask functionality.
+
+/**
+ * rw_mgr_mem_calibrate_write_test_issue() - Issue write test command
+ * @group: Write Group
+ * @use_dm: Use DM
+ *
+ * Issue write test command. Two variants are provided, one that just tests
+ * a write pattern and another that tests datamask functionality.
*/
-static void rw_mgr_mem_calibrate_write_test_issue(uint32_t group,
- uint32_t test_dm)
+static void rw_mgr_mem_calibrate_write_test_issue(u32 group,
+ u32 test_dm)
{
- uint32_t mcc_instruction;
- uint32_t quick_write_mode = (((STATIC_CALIB_STEPS) & CALIB_SKIP_WRITES) &&
- ENABLE_SUPER_QUICK_CALIBRATION);
- uint32_t rw_wl_nop_cycles;
- uint32_t addr;
+ const u32 quick_write_mode =
+ (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES) &&
+ ENABLE_SUPER_QUICK_CALIBRATION;
+ u32 mcc_instruction;
+ u32 rw_wl_nop_cycles;
/*
* Set counter and jump addresses for the right
&sdr_rw_load_jump_mgr_regs->load_jump_add1);
}
- addr = SDR_PHYGRP_RWMGRGRP_ADDRESS | RW_MGR_RUN_SINGLE_GROUP_OFFSET;
- writel(mcc_instruction, addr + (group << 2));
+ writel(mcc_instruction, (SDR_PHYGRP_RWMGRGRP_ADDRESS |
+ RW_MGR_RUN_SINGLE_GROUP_OFFSET) +
+ (group << 2));
}
-/* Test writes, can check for a single bit pass or multiple bit pass */
+/**
+ * rw_mgr_mem_calibrate_write_test() - Test writes, check for single/multiple pass
+ * @rank_bgn: Rank number
+ * @write_group: Write Group
+ * @use_dm: Use DM
+ * @all_correct: All bits must be correct in the mask
+ * @bit_chk: Resulting bit mask after the test
+ * @all_ranks: Test all ranks
+ *
+ * Test writes, can check for a single bit pass or multiple bit pass.
+ */
static int
rw_mgr_mem_calibrate_write_test(const u32 rank_bgn, const u32 write_group,
const u32 use_dm, const u32 all_correct,
return 1;
}
-/* VFIFO Calibration -- Read Deskew Calibration after write deskew */
-static uint32_t rw_mgr_mem_calibrate_vfifo_end(uint32_t read_group,
- uint32_t test_bgn)
+/**
+ * rw_mgr_mem_calibrate_vfifo_end() - DQ/DQS Centering.
+ * @rw_group: Read/Write Group
+ * @test_bgn: Rank at which the test begins
+ *
+ * Stage 3: DQ/DQS Centering.
+ *
+ * This function implements UniPHY calibration Stage 3, as explained in
+ * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
+ */
+static int rw_mgr_mem_calibrate_vfifo_end(const u32 rw_group,
+ const u32 test_bgn)
{
- uint32_t rank_bgn, sr;
- uint32_t grp_calibrated;
- uint32_t write_group;
-
- debug("%s:%d %u %u", __func__, __LINE__, read_group, test_bgn);
+ int ret;
- /* update info for sims */
+ debug("%s:%d %u %u", __func__, __LINE__, rw_group, test_bgn);
+ /* Update info for sims. */
+ reg_file_set_group(rw_group);
reg_file_set_stage(CAL_STAGE_VFIFO_AFTER_WRITES);
reg_file_set_sub_stage(CAL_SUBSTAGE_VFIFO_CENTER);
- write_group = read_group;
-
- /* update info for sims */
- reg_file_set_group(read_group);
-
- grp_calibrated = 1;
- /* Read per-bit deskew can be done on a per shadow register basis */
- for (rank_bgn = 0, sr = 0; rank_bgn < RW_MGR_MEM_NUMBER_OF_RANKS;
- rank_bgn += NUM_RANKS_PER_SHADOW_REG, ++sr) {
- /* Determine if this set of ranks should be skipped entirely */
- if (!param->skip_shadow_regs[sr]) {
- /* This is the last calibration round, update FOM here */
- if (rw_mgr_mem_calibrate_vfifo_center(rank_bgn,
- read_group,
- test_bgn, 0,
- 1)) {
- grp_calibrated = 0;
- }
- }
- }
-
-
- if (grp_calibrated == 0) {
- set_failing_group_stage(write_group,
+ ret = rw_mgr_mem_calibrate_dq_dqs_centering(rw_group, test_bgn, 0, 1);
+ if (ret)
+ set_failing_group_stage(rw_group,
CAL_STAGE_VFIFO_AFTER_WRITES,
CAL_SUBSTAGE_VFIFO_CENTER);
- return 0;
- }
-
- return 1;
+ return ret;
}
-/* Calibrate LFIFO to find smallest read latency */
+/**
+ * rw_mgr_mem_calibrate_lfifo() - Minimize latency
+ *
+ * Stage 4: Minimize latency.
+ *
+ * This function implements UniPHY calibration Stage 4, as explained in
+ * detail in Altera EMI_RM 2015.05.04 , "UniPHY Calibration Stages".
+ * Calibrate LFIFO to find smallest read latency.
+ */
static uint32_t rw_mgr_mem_calibrate_lfifo(void)
{
- uint32_t found_one;
+ int found_one = 0;
debug("%s:%d\n", __func__, __LINE__);
- /* update info for sims */
+ /* Update info for sims. */
reg_file_set_stage(CAL_STAGE_LFIFO);
reg_file_set_sub_stage(CAL_SUBSTAGE_READ_LATENCY);
/* Load up the patterns used by read calibration for all ranks */
rw_mgr_mem_calibrate_read_load_patterns(0, 1);
- found_one = 0;
do {
writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
debug_cond(DLEVEL == 2, "%s:%d lfifo: read_lat=%u",
__func__, __LINE__, gbl->curr_read_lat);
- if (!rw_mgr_mem_calibrate_read_test_all_ranks(0,
- NUM_READ_TESTS,
- PASS_ALL_BITS,
- 1)) {
+ if (!rw_mgr_mem_calibrate_read_test_all_ranks(0, NUM_READ_TESTS,
+ PASS_ALL_BITS, 1))
break;
- }
found_one = 1;
- /* reduce read latency and see if things are working */
- /* correctly */
+ /*
+ * Reduce read latency and see if things are
+ * working correctly.
+ */
gbl->curr_read_lat--;
} while (gbl->curr_read_lat > 0);
- /* reset the fifos to get pointers to known state */
-
+ /* Reset the fifos to get pointers to known state. */
writel(0, &phy_mgr_cmd->fifo_reset);
if (found_one) {
- /* add a fudge factor to the read latency that was determined */
+ /* Add a fudge factor to the read latency that was determined */
gbl->curr_read_lat += 2;
writel(gbl->curr_read_lat, &phy_mgr_cfg->phy_rlat);
- debug_cond(DLEVEL == 2, "%s:%d lfifo: success: using \
- read_lat=%u\n", __func__, __LINE__,
- gbl->curr_read_lat);
- return 1;
+ debug_cond(DLEVEL == 2,
+ "%s:%d lfifo: success: using read_lat=%u\n",
+ __func__, __LINE__, gbl->curr_read_lat);
} else {
set_failing_group_stage(0xff, CAL_STAGE_LFIFO,
CAL_SUBSTAGE_READ_LATENCY);
- debug_cond(DLEVEL == 2, "%s:%d lfifo: failed at initial \
- read_lat=%u\n", __func__, __LINE__,
- gbl->curr_read_lat);
- return 0;
+ debug_cond(DLEVEL == 2,
+ "%s:%d lfifo: failed at initial read_lat=%u\n",
+ __func__, __LINE__, gbl->curr_read_lat);
}
+
+ return found_one;
}
/**
if (STATIC_CALIB_STEPS & CALIB_SKIP_WRITES)
continue;
- if (rw_mgr_mem_calibrate_vfifo_end(read_group,
+ if (!rw_mgr_mem_calibrate_vfifo_end(read_group,
read_test_bgn))
continue;
projects / karo-tx-uboot.git / blobdiff