fsl/sleep: updated the deep sleep framework for QorIQ platforms

[karo-tx-uboot.git] / drivers / ddr / fsl / mpc85xx_ddr_gen3.c

diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
index 4d5572ef21b65b0d68c3524bc8f48038b0a261cc..8f4d01ad856b22a269e0c6df363429e605cf7877 100644 (file)
--- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
+++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c
@@ -15,8 +15,6 @@
 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
 #endif
 
-DECLARE_GLOBAL_DATA_PTR;
-
 /*
  * regs has the to-be-set values for DDR controller registers
  * ctrl_num is the DDR controller number
@@ -44,16 +42,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        u32 save1, save2;
 #endif
 
-#ifdef CONFIG_DEEP_SLEEP
-       const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-       bool sleep_flag = 0;
-#endif
-
-#ifdef CONFIG_DEEP_SLEEP
-       if (in_be32(&gur->scrtsr[0]) & (1 << 3))
-               sleep_flag = 1;
-#endif
-
        switch (ctrl_num) {
        case 0:
                ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
@@ -130,13 +118,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
        out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
        out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
-#ifdef CONFIG_DEEP_SLEEP
-       if (sleep_flag)
-               out_be32(&ddr->sdram_cfg_2,
-                        regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
-       else
-#endif
-               out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
        out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
        out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
        out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
@@ -149,17 +130,6 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
        out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
        out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
-#ifdef CONFIG_DEEP_SLEEP
-       if (sleep_flag) {
-               out_be32(&ddr->init_addr, 0);
-               out_be32(&ddr->init_ext_addr, (1 << 31));
-       } else
-#endif
-       {
-               out_be32(&ddr->init_addr, regs->ddr_init_addr);
-               out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
-       }
-
        out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4);
        out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
        out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
@@ -180,7 +150,24 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
        out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
        out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1);
-       out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2);
+#ifdef CONFIG_DEEP_SLEEP
+       if (is_warm_boot()) {
+               out_be32(&ddr->sdram_cfg_2,
+                        regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
+               out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
+               out_be32(&ddr->init_ext_addr, DDR_INIT_ADDR_EXT_UIA);
+
+               /* DRAM VRef will not be trained */
+               out_be32(&ddr->ddr_cdr2,
+                        regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
+       } else
+#endif
+       {
+               out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
+               out_be32(&ddr->init_addr, regs->ddr_init_addr);
+               out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
+               out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2);
+       }
        out_be32(&ddr->err_disable, regs->err_disable);
        out_be32(&ddr->err_int_en, regs->err_int_en);
        for (i = 0; i < 32; i++) {
@@ -400,21 +387,17 @@ step2:
        asm volatile("sync;isync");
 
 #ifdef CONFIG_DEEP_SLEEP
-       if (sleep_flag) {
+       if (is_warm_boot()) {
                /* enter self-refresh */
-               setbits_be32(&ddr->sdram_cfg_2, (1 << 31));
+               setbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR);
                /* do board specific memory setup */
                board_mem_sleep_setup();
-       }
-#endif
-
-       /* Let the controller go */
-#ifdef CONFIG_DEEP_SLEEP
-       if (sleep_flag)
                temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
-       else
+       } else
 #endif
                temp_sdram_cfg = (in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI);
+
+       /* Let the controller go */
        out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
        asm volatile("sync;isync");
 
@@ -566,8 +549,8 @@ step2:
        }
 #endif /* CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 */
 #ifdef CONFIG_DEEP_SLEEP
-       if (sleep_flag)
+       if (is_warm_boot())
                /* exit self-refresh */
-               clrbits_be32(&ddr->sdram_cfg_2, (1 << 31));
+               clrbits_be32(&ddr->sdram_cfg_2, SDRAM_CFG2_FRC_SR);
 #endif
 }