Merge branch 'next' into for-linus

[karo-tx-linux.git] / drivers / dma / ste_dma40_ll.h

diff --git a/drivers/dma/ste_dma40_ll.h b/drivers/dma/ste_dma40_ll.h
index 6d47373f3f5893c86fad20976285138faaaf3758..fdde8ef775422fff777eff169a8b39733b72af43 100644 (file)
--- a/drivers/dma/ste_dma40_ll.h
+++ b/drivers/dma/ste_dma40_ll.h
@@ -125,7 +125,7 @@
 #define D40_DREG_GCC           0x000
 #define D40_DREG_GCC_ENA       0x1
 /* This assumes that there are only 4 event groups */
-#define D40_DREG_GCC_ENABLE_ALL        0xff01
+#define D40_DREG_GCC_ENABLE_ALL        0x3ff01
 #define D40_DREG_GCC_EVTGRP_POS 8
 #define D40_DREG_GCC_SRC 0
 #define D40_DREG_GCC_DST 1
@@ -148,14 +148,31 @@
 
 #define D40_DREG_LCPA          0x020
 #define D40_DREG_LCLA          0x024
+
+#define D40_DREG_SSEG1         0x030
+#define D40_DREG_SSEG2         0x034
+#define D40_DREG_SSEG3         0x038
+#define D40_DREG_SSEG4         0x03C
+
+#define D40_DREG_SCEG1         0x040
+#define D40_DREG_SCEG2         0x044
+#define D40_DREG_SCEG3         0x048
+#define D40_DREG_SCEG4         0x04C
+
 #define D40_DREG_ACTIVE                0x050
 #define D40_DREG_ACTIVO                0x054
-#define D40_DREG_FSEB1         0x058
-#define D40_DREG_FSEB2         0x05C
+#define D40_DREG_CIDMOD                0x058
+#define D40_DREG_TCIDV         0x05C
 #define D40_DREG_PCMIS         0x060
 #define D40_DREG_PCICR         0x064
 #define D40_DREG_PCTIS         0x068
 #define D40_DREG_PCEIS         0x06C
+
+#define D40_DREG_SPCMIS                0x070
+#define D40_DREG_SPCICR                0x074
+#define D40_DREG_SPCTIS                0x078
+#define D40_DREG_SPCEIS                0x07C
+
 #define D40_DREG_LCMIS0                0x080
 #define D40_DREG_LCMIS1                0x084
 #define D40_DREG_LCMIS2                0x088
@@ -172,6 +189,33 @@
 #define D40_DREG_LCEIS1                0x0B4
 #define D40_DREG_LCEIS2                0x0B8
 #define D40_DREG_LCEIS3                0x0BC
+
+#define D40_DREG_SLCMIS1       0x0C0
+#define D40_DREG_SLCMIS2       0x0C4
+#define D40_DREG_SLCMIS3       0x0C8
+#define D40_DREG_SLCMIS4       0x0CC
+
+#define D40_DREG_SLCICR1       0x0D0
+#define D40_DREG_SLCICR2       0x0D4
+#define D40_DREG_SLCICR3       0x0D8
+#define D40_DREG_SLCICR4       0x0DC
+
+#define D40_DREG_SLCTIS1       0x0E0
+#define D40_DREG_SLCTIS2       0x0E4
+#define D40_DREG_SLCTIS3       0x0E8
+#define D40_DREG_SLCTIS4       0x0EC
+
+#define D40_DREG_SLCEIS1       0x0F0
+#define D40_DREG_SLCEIS2       0x0F4
+#define D40_DREG_SLCEIS3       0x0F8
+#define D40_DREG_SLCEIS4       0x0FC
+
+#define D40_DREG_FSESS1                0x100
+#define D40_DREG_FSESS2                0x104
+
+#define D40_DREG_FSEBS1                0x108
+#define D40_DREG_FSEBS2                0x10C
+
 #define D40_DREG_PSEG1         0x110
 #define D40_DREG_PSEG2         0x114
 #define D40_DREG_PSEG3         0x118
@@ -188,6 +232,86 @@
 #define D40_DREG_RCEG2         0x144
 #define D40_DREG_RCEG3         0x148
 #define D40_DREG_RCEG4         0x14C
+
+#define D40_DREG_PREFOT                0x15C
+#define D40_DREG_EXTCFG                0x160
+
+#define D40_DREG_CPSEG1                0x200
+#define D40_DREG_CPSEG2                0x204
+#define D40_DREG_CPSEG3                0x208
+#define D40_DREG_CPSEG4                0x20C
+#define D40_DREG_CPSEG5                0x210
+
+#define D40_DREG_CPCEG1                0x220
+#define D40_DREG_CPCEG2                0x224
+#define D40_DREG_CPCEG3                0x228
+#define D40_DREG_CPCEG4                0x22C
+#define D40_DREG_CPCEG5                0x230
+
+#define D40_DREG_CRSEG1                0x240
+#define D40_DREG_CRSEG2                0x244
+#define D40_DREG_CRSEG3                0x248
+#define D40_DREG_CRSEG4                0x24C
+#define D40_DREG_CRSEG5                0x250
+
+#define D40_DREG_CRCEG1                0x260
+#define D40_DREG_CRCEG2                0x264
+#define D40_DREG_CRCEG3                0x268
+#define D40_DREG_CRCEG4                0x26C
+#define D40_DREG_CRCEG5                0x270
+
+#define D40_DREG_CFSESS1       0x280
+#define D40_DREG_CFSESS2       0x284
+#define D40_DREG_CFSESS3       0x288
+
+#define D40_DREG_CFSEBS1       0x290
+#define D40_DREG_CFSEBS2       0x294
+#define D40_DREG_CFSEBS3       0x298
+
+#define D40_DREG_CLCMIS1       0x300
+#define D40_DREG_CLCMIS2       0x304
+#define D40_DREG_CLCMIS3       0x308
+#define D40_DREG_CLCMIS4       0x30C
+#define D40_DREG_CLCMIS5       0x310
+
+#define D40_DREG_CLCICR1       0x320
+#define D40_DREG_CLCICR2       0x324
+#define D40_DREG_CLCICR3       0x328
+#define D40_DREG_CLCICR4       0x32C
+#define D40_DREG_CLCICR5       0x330
+
+#define D40_DREG_CLCTIS1       0x340
+#define D40_DREG_CLCTIS2       0x344
+#define D40_DREG_CLCTIS3       0x348
+#define D40_DREG_CLCTIS4       0x34C
+#define D40_DREG_CLCTIS5       0x350
+
+#define D40_DREG_CLCEIS1       0x360
+#define D40_DREG_CLCEIS2       0x364
+#define D40_DREG_CLCEIS3       0x368
+#define D40_DREG_CLCEIS4       0x36C
+#define D40_DREG_CLCEIS5       0x370
+
+#define D40_DREG_CPCMIS                0x380
+#define D40_DREG_CPCICR                0x384
+#define D40_DREG_CPCTIS                0x388
+#define D40_DREG_CPCEIS                0x38C
+
+#define D40_DREG_SCCIDA1       0xE80
+#define D40_DREG_SCCIDA2       0xE90
+#define D40_DREG_SCCIDA3       0xEA0
+#define D40_DREG_SCCIDA4       0xEB0
+#define D40_DREG_SCCIDA5       0xEC0
+
+#define D40_DREG_SCCIDB1       0xE84
+#define D40_DREG_SCCIDB2       0xE94
+#define D40_DREG_SCCIDB3       0xEA4
+#define D40_DREG_SCCIDB4       0xEB4
+#define D40_DREG_SCCIDB5       0xEC4
+
+#define D40_DREG_PRSCCIDA      0xF80
+#define D40_DREG_PRSCCIDB      0xF84
+
 #define D40_DREG_STFU          0xFC8
 #define D40_DREG_ICFG          0xFCC
 #define D40_DREG_PERIPHID0     0xFE0