#include <linux/slab.h>
#include <linux/edac.h>
#include <linux/mmzone.h>
+#include <linux/edac_mce.h>
+#include <linux/spinlock.h>
#include "edac_core.h"
#define MC_DOD_NUMBANK(x) (((x) & MC_DOD_NUMBANK_MASK) >> 7)
#define MC_DOD_NUMRANK_MASK ((1 << 6) | (1 << 5))
#define MC_DOD_NUMRANK(x) (((x) & MC_DOD_NUMRANK_MASK) >> 5)
- #define MC_DOD_NUMROW_MASK ((1 << 4) | (1 << 3))
- #define MC_DOD_NUMROW(x) (((x) & MC_DOD_NUMROW_MASK) >> 3)
+ #define MC_DOD_NUMROW_MASK ((1 << 4) | (1 << 3) | (1 << 2))
+ #define MC_DOD_NUMROW(x) (((x) & MC_DOD_NUMROW_MASK) >> 2)
#define MC_DOD_NUMCOL_MASK 3
#define MC_DOD_NUMCOL(x) ((x) & MC_DOD_NUMCOL_MASK)
unsigned long ce_count[MAX_DIMMS]; /* ECC corrected errors counts per dimm */
int last_ce_count[MAX_DIMMS];
+ /* mcelog glue */
+ struct edac_mce edac_mce;
+ struct mce mce_entry[MCE_LOG_LEN];
+ unsigned mce_count;
+ spinlock_t mce_lock;
};
/* Device name and register DID (Device ID) */
/****************************************************************************
Memory check routines
****************************************************************************/
-static int i7core_get_active_channels(int *channels)
+static struct pci_dev *get_pdev_slot_func(int slot, int func)
{
- struct pci_dev *pdev = NULL;
int i;
- u32 status, control;
-
- *channels = 0;
for (i = 0; i < N_DEVS; i++) {
if (!pci_devs[i].pdev)
continue;
- if (PCI_SLOT(pci_devs[i].pdev->devfn) == 3 &&
- PCI_FUNC(pci_devs[i].pdev->devfn) == 0) {
- pdev = pci_devs[i].pdev;
- break;
+ if (PCI_SLOT(pci_devs[i].pdev->devfn) == slot &&
+ PCI_FUNC(pci_devs[i].pdev->devfn) == func) {
+ return pci_devs[i].pdev;
}
}
+ return NULL;
+}
+
+static int i7core_get_active_channels(int *channels, int *csrows)
+{
+ struct pci_dev *pdev = NULL;
+ int i, j;
+ u32 status, control;
+
+ *channels = 0;
+ *csrows = 0;
+
+ pdev = get_pdev_slot_func(3, 0);
if (!pdev) {
i7core_printk(KERN_ERR, "Couldn't find fn 3.0!!!\n");
return -ENODEV;
pci_read_config_dword(pdev, MC_CONTROL, &control);
for (i = 0; i < NUM_CHANS; i++) {
+ u32 dimm_dod[3];
/* Check if the channel is active */
if (!(control & (1 << (8 + i))))
continue;
/* Check if the channel is disabled */
- if (status & (1 << i)) {
+ if (status & (1 << i))
continue;
+
+ pdev = get_pdev_slot_func(i + 4, 1);
+ if (!pdev) {
+ i7core_printk(KERN_ERR, "Couldn't find fn %d.%d!!!\n",
+ i + 4, 1);
+ return -ENODEV;
}
+ /* Devices 4-6 function 1 */
+ pci_read_config_dword(pdev,
+ MC_DOD_CH_DIMM0, &dimm_dod[0]);
+ pci_read_config_dword(pdev,
+ MC_DOD_CH_DIMM1, &dimm_dod[1]);
+ pci_read_config_dword(pdev,
+ MC_DOD_CH_DIMM2, &dimm_dod[2]);
(*channels)++;
+
+ for (j = 0; j < 3; j++) {
+ if (!DIMM_PRESENT(dimm_dod[j]))
+ continue;
+ (*csrows)++;
+ }
}
debugf0("Number of active channels: %d\n", *channels);
struct csrow_info *csr;
struct pci_dev *pdev;
int i, j, csrow = 0;
+ unsigned long last_page = 0;
enum edac_type mode;
enum mem_type mtype;
pvt->info.max_dod, pvt->info.ch_map);
if (ECC_ENABLED(pvt)) {
- debugf0("ECC enabled with x%d SDCC\n", ECCx8(pvt)?8:4);
+ debugf0("ECC enabled with x%d SDCC\n", ECCx8(pvt) ? 8 : 4);
if (ECCx8(pvt))
mode = EDAC_S8ECD8ED;
else
pci_read_config_dword(pvt->pci_ch[i][0],
MC_CHANNEL_DIMM_INIT_PARAMS, &data);
- pvt->channel[i].ranks = (data & QUAD_RANK_PRESENT)? 4 : 2;
+ pvt->channel[i].ranks = (data & QUAD_RANK_PRESENT) ? 4 : 2;
if (data & REGISTERED_DIMM)
mtype = MEM_RDDR3;
RDLCH(pvt->info.ch_map, i), WRLCH(pvt->info.ch_map, i),
data,
pvt->channel[i].ranks,
- (data & REGISTERED_DIMM)? 'R' : 'U');
+ (data & REGISTERED_DIMM) ? 'R' : 'U');
for (j = 0; j < 3; j++) {
u32 banks, ranks, rows, cols;
+ u32 size, npages;
if (!DIMM_PRESENT(dimm_dod[j]))
continue;
rows = numrow(MC_DOD_NUMROW(dimm_dod[j]));
cols = numcol(MC_DOD_NUMCOL(dimm_dod[j]));
+ /* DDR3 has 8 I/O banks */
+ size = (rows * cols * banks * ranks) >> (20 - 3);
+
pvt->channel[i].dimms++;
- debugf0("\tdimm %d offset: %x, numbank: %#x, "
- "numrank: %#x, numrow: %#x, numcol: %#x\n",
- j,
+ debugf0("\tdimm %d (0x%08x) %d Mb offset: %x, "
+ "numbank: %d,\n\t\t"
+ "numrank: %d, numrow: %#x, numcol: %#x\n",
+ j, dimm_dod[j], size,
RANKOFFSET(dimm_dod[j]),
banks, ranks, rows, cols);
+#if PAGE_SHIFT > 20
+ npages = size >> (PAGE_SHIFT - 20);
+#else
+ npages = size << (20 - PAGE_SHIFT);
+#endif
+
csr = &mci->csrows[csrow];
- csr->first_page = 0;
- csr->last_page = 0;
+ csr->first_page = last_page + 1;
+ last_page += npages;
+ csr->last_page = last_page;
+ csr->nr_pages = npages;
+
csr->page_mask = 0;
- csr->nr_pages = 0;
- csr->grain = 0;
+ csr->grain = 8;
csr->csrow_idx = csrow;
+ csr->nr_channels = 1;
+
+ csr->channels[0].chan_idx = i;
+ csr->channels[0].ce_count = 0;
switch (banks) {
case 4:
pci_read_config_dword(pdev, MC_SAG_CH_5, &value[5]);
pci_read_config_dword(pdev, MC_SAG_CH_6, &value[6]);
pci_read_config_dword(pdev, MC_SAG_CH_7, &value[7]);
- printk("\t[%i] DIVBY3\tREMOVED\tOFFSET\n", i);
+ debugf0("\t[%i] DIVBY3\tREMOVED\tOFFSET\n", i);
for (j = 0; j < 8; j++)
- printk("\t\t%#x\t%#x\t%#x\n",
+ debugf0("\t\t%#x\t%#x\t%#x\n",
(value[j] >> 27) & 0x1,
(value[j] >> 24) & 0x7,
(value[j] && ((1 << 24) - 1)));
int rc;
if (pvt->inject.enable)
- disable_inject(mci);
+ disable_inject(mci);
rc = strict_strtoul(data, 10, &value);
if ((rc < 0) || (value > 3))
int rc;
if (pvt->inject.enable)
- disable_inject(mci);
+ disable_inject(mci);
rc = strict_strtoul(data, 10, &value);
if ((rc < 0) || (value > 7))
int rc;
if (pvt->inject.enable)
- disable_inject(mci);
+ disable_inject(mci);
rc = strict_strtoul(data, 10, &value);
if (rc < 0)
int rc;
if (pvt->inject.enable)
- disable_inject(mci);
+ disable_inject(mci);
do {
cmd = strsep((char **) &data, ":");
if (!val)
return cmd - data;
- if (!strcasecmp(val,"any"))
+ if (!strcasecmp(val, "any"))
value = -1;
else {
rc = strict_strtol(val, 10, &value);
return cmd - data;
}
- if (!strcasecmp(cmd,"channel")) {
+ if (!strcasecmp(cmd, "channel")) {
if (value < 3)
pvt->inject.channel = value;
else
return cmd - data;
- } else if (!strcasecmp(cmd,"dimm")) {
+ } else if (!strcasecmp(cmd, "dimm")) {
if (value < 4)
pvt->inject.dimm = value;
else
return cmd - data;
- } else if (!strcasecmp(cmd,"rank")) {
+ } else if (!strcasecmp(cmd, "rank")) {
if (value < 4)
pvt->inject.rank = value;
else
return cmd - data;
- } else if (!strcasecmp(cmd,"bank")) {
+ } else if (!strcasecmp(cmd, "bank")) {
if (value < 4)
pvt->inject.bank = value;
else
return cmd - data;
- } else if (!strcasecmp(cmd,"page")) {
+ } else if (!strcasecmp(cmd, "page")) {
if (value <= 0xffff)
pvt->inject.page = value;
else
return cmd - data;
- } else if (!strcasecmp(cmd,"col") ||
- !strcasecmp(cmd,"column")) {
+ } else if (!strcasecmp(cmd, "col") ||
+ !strcasecmp(cmd, "column")) {
if (value <= 0x3fff)
pvt->inject.col = value;
else
pci_read_config_dword(pvt->pci_ch[pvt->inject.channel][0],
MC_CHANNEL_ADDR_MATCH + 4, &rdmask2);
- debugf0("Inject addr match write 0x%016llx, read: 0x%08x%08x\n",
+ debugf0("Inject addr match write 0x%016llx, read: 0x%08x 0x%08x\n",
mask, rdmask1, rdmask2);
#endif
#endif
pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0],
MC_CHANNEL_ERROR_MASK, injectmask);
- debugf0("Error inject addr match 0x%016llx, ecc 0x%08x, inject 0x%08x\n",
+ debugf0("Error inject addr match 0x%016llx, ecc 0x%08x,"
+ " inject 0x%08x\n",
mask, pvt->inject.eccmask, injectmask);
"Device not found: PCI ID %04x:%04x "
"(dev %d, func %d)\n",
PCI_VENDOR_ID_INTEL, pci_devs[i].dev_id,
- pci_devs[i].dev,pci_devs[i].func);
+ pci_devs[i].dev, pci_devs[i].func);
/* Dev 3 function 2 only exists on chips with RDIMMs */
if ((pci_devs[i].dev == 3) && (pci_devs[i].func == 2))
new1 = DIMM1_COR_ERR(rcv0);
new0 = DIMM0_COR_ERR(rcv0);
+#if 0
debugf2("%s CE rcv1=0x%08x rcv0=0x%08x, %d %d %d\n",
(pvt->ce_count_available ? "UPDATE" : "READ"),
rcv1, rcv0, new0, new1, new2);
+#endif
/* Updates CE counters if it is not the first time here */
if (pvt->ce_count_available) {
pvt->last_ce_count[0] = new0;
}
+static void i7core_mce_output_error(struct mem_ctl_info *mci,
+ struct mce *m)
+{
+ debugf0("CPU %d: Machine Check Exception: %16Lx"
+ "Bank %d: %016Lx\n",
+ m->cpu, m->mcgstatus, m->bank, m->status);
+ if (m->ip) {
+ debugf0("RIP%s %02x:<%016Lx>\n",
+ !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
+ m->cs, m->ip);
+ }
+ printk(KERN_EMERG "TSC %llx ", m->tsc);
+ if (m->addr)
+ printk("ADDR %llx ", m->addr);
+ if (m->misc)
+ printk("MISC %llx ", m->misc);
+
+#if 0
+ snprintf(msg, sizeof(msg),
+ "%s (Branch=%d DRAM-Bank=%d Buffer ID = %d RDWR=%s "
+ "RAS=%d CAS=%d %s Err=0x%lx (%s))",
+ type, branch >> 1, bank, buf_id, rdwr_str(rdwr), ras, cas,
+ type, allErrors, error_name[errnum]);
+
+ /* Call the helper to output message */
+ edac_mc_handle_fbd_ue(mci, rank, channel, channel + 1, msg);
+#endif
+}
+
/*
* i7core_check_error Retrieve and process errors reported by the
* hardware. Called by the Core module.
*/
static void i7core_check_error(struct mem_ctl_info *mci)
{
+ struct i7core_pvt *pvt = mci->pvt_info;
+ int i;
+ unsigned count = 0;
+ struct mce *m = NULL;
+ unsigned long flags;
+
+ debugf0(__FILE__ ": %s()\n", __func__);
+
+ /* Copy all mce errors into a temporary buffer */
+ spin_lock_irqsave(&pvt->mce_lock, flags);
+ if (pvt->mce_count) {
+ m = kmalloc(sizeof(*m) * pvt->mce_count, GFP_ATOMIC);
+ if (m) {
+ count = pvt->mce_count;
+ memcpy(m, &pvt->mce_entry, sizeof(*m) * count);
+ }
+ pvt->mce_count = 0;
+ }
+ spin_unlock_irqrestore(&pvt->mce_lock, flags);
+
+ /* proccess mcelog errors */
+ for (i = 0; i < count; i++)
+ i7core_mce_output_error(mci, &m[i]);
+
+ kfree(m);
+
+ /* check memory count errors */
check_mc_test_err(mci);
}
+/*
+ * i7core_mce_check_error Replicates mcelog routine to get errors
+ * This routine simply queues mcelog errors, and
+ * return. The error itself should be handled later
+ * by i7core_check_error.
+ */
+static int i7core_mce_check_error(void *priv, struct mce *mce)
+{
+ struct i7core_pvt *pvt = priv;
+ unsigned long flags;
+
+ debugf0(__FILE__ ": %s()\n", __func__);
+
+ spin_lock_irqsave(&pvt->mce_lock, flags);
+ if (pvt->mce_count < MCE_LOG_LEN) {
+ memcpy(&pvt->mce_entry[pvt->mce_count], mce, sizeof(*mce));
+ pvt->mce_count++;
+ }
+ spin_unlock_irqrestore(&pvt->mce_lock, flags);
+
+ /* Advice mcelog that the error were handled */
+// return 1;
+ return 0; // Let's duplicate the log
+}
+
/*
* i7core_probe Probe for ONE instance of device to see if it is
* present.
{
struct mem_ctl_info *mci;
struct i7core_pvt *pvt;
- int num_channels = 0;
+ int num_channels;
int num_csrows;
int dev_idx = id->driver_data;
int rc;
return rc;
/* Check the number of active and not disabled channels */
- rc = i7core_get_active_channels(&num_channels);
- if (unlikely (rc < 0))
+ rc = i7core_get_active_channels(&num_channels, &num_csrows);
+ if (unlikely(rc < 0))
goto fail0;
- /* FIXME: we currently don't know the number of csrows */
- num_csrows = num_channels;
-
/* allocate a new MC control structure */
mci = edac_mc_alloc(sizeof(*pvt), num_csrows, num_channels, 0);
- if (unlikely (!mci)) {
+ if (unlikely(!mci)) {
rc = -ENOMEM;
goto fail0;
}
memset(pvt, 0, sizeof(*pvt));
mci->mc_idx = 0;
- mci->mtype_cap = MEM_FLAG_DDR3; /* FIXME: how to handle RDDR3? */
+ /*
+ * FIXME: how to handle RDDR3 at MCI level? It is possible to have
+ * Mixed RDDR3/UDDR3 with Nehalem, provided that they are on different
+ * memory channels
+ */
+ mci->mtype_cap = MEM_FLAG_DDR3;
mci->edac_ctl_cap = EDAC_FLAG_NONE;
mci->edac_cap = EDAC_FLAG_NONE;
mci->mod_name = "i7core_edac.c";
/* Store pci devices at mci for faster access */
rc = mci_bind_devs(mci);
- if (unlikely (rc < 0))
+ if (unlikely(rc < 0))
goto fail1;
/* Get dimm basic config */
/* allocating generic PCI control info */
i7core_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
- if (unlikely (!i7core_pci)) {
+ if (unlikely(!i7core_pci)) {
printk(KERN_WARNING
"%s(): Unable to create PCI control\n",
__func__);
pvt->inject.page = -1;
pvt->inject.col = -1;
+ /* Registers on edac_mce in order to receive memory errors */
+ pvt->edac_mce.priv = pvt;
+ pvt->edac_mce.check_error = i7core_mce_check_error;
+ spin_lock_init(&pvt->mce_lock);
+
+ rc = edac_mce_register(&pvt->edac_mce);
+ if (unlikely (rc < 0)) {
+ debugf0("MC: " __FILE__
+ ": %s(): failed edac_mce_register()\n", __func__);
+ goto fail1;
+ }
+
i7core_printk(KERN_INFO, "Driver loaded.\n");
return 0;
static void __devexit i7core_remove(struct pci_dev *pdev)
{
struct mem_ctl_info *mci;
+ struct i7core_pvt *pvt;
debugf0(__FILE__ ": %s()\n", __func__);
if (i7core_pci)
edac_pci_release_generic_ctl(i7core_pci);
- mci = edac_mc_del_mc(&pdev->dev);
+ mci = edac_mc_del_mc(&pdev->dev);
if (!mci)
return;
+ /* Unregisters on edac_mce in order to receive memory errors */
+ pvt = mci->pvt_info;
+ edac_mce_unregister(&pvt->edac_mce);
+
/* retrieve references to resources, and free those resources */
i7core_put_devices();
projects / karo-tx-linux.git / blobdiff