if (ret)
return ret;
+ mvebu_gpio_set(chip, pin, value);
+
spin_lock_irqsave(&mvchip->lock, flags);
u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip));
u &= ~(1 << pin);
u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
u &= ~(1 << pin);
writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
+ break;
case IRQ_TYPE_EDGE_FALLING:
case IRQ_TYPE_LEVEL_LOW:
u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
u |= 1 << pin;
writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
+ break;
case IRQ_TYPE_EDGE_BOTH: {
u32 v;
else
u &= ~(1 << pin); /* rising */
writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
+ break;
}
}
return 0;
ct->handler = handle_edge_irq;
ct->chip.name = mvchip->chip.label;
- irq_setup_generic_chip(gc, IRQ_MSK(ngpios), IRQ_GC_INIT_MASK_CACHE,
+ irq_setup_generic_chip(gc, IRQ_MSK(ngpios), 0,
IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
/* Setup irq domain on top of the generic chip. */