Merge branch 'drm-next-4.4' of git://people.freedesktop.org/~agd5f/linux into drm...

[karo-tx-linux.git] / drivers / gpu / drm / amd / amdgpu / dce_v11_0.c

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index 5be83a3f019210fa87ee3840d5c1eb74f6cc3dce..784afb5978acd154d5ac8ff20851826c10e49dc2 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -126,6 +126,13 @@ static const u32 cz_mgcg_cgcg_init[] =
        mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
 };
 
+static const u32 stoney_golden_settings_a11[] =
+{
+       mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
+       mmFBC_MISC, 0x1f311fff, 0x14302000,
+};
+
+
 static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
 {
        switch (adev->asic_type) {
@@ -137,6 +144,11 @@ static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
                                                 cz_golden_settings_a11,
                                                 (const u32)ARRAY_SIZE(cz_golden_settings_a11));
                break;
+       case CHIP_STONEY:
+               amdgpu_program_register_sequence(adev,
+                                                stoney_golden_settings_a11,
+                                                (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
+               break;
        default:
                break;
        }
@@ -2425,7 +2437,7 @@ static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
 
        /* XXX need to determine what plls are available on each DCE11 part */
        pll_in_use = amdgpu_pll_get_use_mask(crtc);
-       if (adev->asic_type == CHIP_CARRIZO) {
+       if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) {
                if (!(pll_in_use & (1 << ATOM_PPLL1)))
                        return ATOM_PPLL1;
                if (!(pll_in_use & (1 << ATOM_PPLL0)))
@@ -2930,6 +2942,11 @@ static int dce_v11_0_early_init(void *handle)
                adev->mode_info.num_hpd = 6;
                adev->mode_info.num_dig = 9;
                break;
+       case CHIP_STONEY:
+               adev->mode_info.num_crtc = 2;
+               adev->mode_info.num_hpd = 6;
+               adev->mode_info.num_dig = 9;
+               break;
        default:
                /* FIXME: not supported yet */
                return -EINVAL;
@@ -3028,6 +3045,7 @@ static int dce_v11_0_hw_init(void *handle)
        dce_v11_0_init_golden_registers(adev);
 
        /* init dig PHYs, disp eng pll */
+       amdgpu_atombios_crtc_powergate_init(adev);
        amdgpu_atombios_encoder_init_dig(adev);
        amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
 
@@ -3061,23 +3079,18 @@ static int dce_v11_0_suspend(void *handle)
 
        amdgpu_atombios_scratch_regs_save(adev);
 
-       dce_v11_0_hpd_fini(adev);
-
-       return 0;
+       return dce_v11_0_hw_fini(handle);
 }
 
 static int dce_v11_0_resume(void *handle)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       int ret;
 
-       dce_v11_0_init_golden_registers(adev);
+       ret = dce_v11_0_hw_init(handle);
 
        amdgpu_atombios_scratch_regs_restore(adev);
 
-       /* init dig PHYs, disp eng pll */
-       amdgpu_atombios_crtc_powergate_init(adev);
-       amdgpu_atombios_encoder_init_dig(adev);
-       amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
        /* turn on the BL */
        if (adev->mode_info.bl_encoder) {
                u8 bl_level = amdgpu_display_backlight_get_level(adev,
@@ -3086,10 +3099,7 @@ static int dce_v11_0_resume(void *handle)
                                                    bl_level);
        }
 
-       /* initialize hpd */
-       dce_v11_0_hpd_init(adev);
-
-       return 0;
+       return ret;
 }
 
 static bool dce_v11_0_is_idle(void *handle)