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drm/amdgpu: update golden setting/tiling table of tahiti
[karo-tx-linux.git] / drivers / gpu / drm / amd / amdgpu / si.c
diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index dc9511c5ecb8ea393cc3097a9507b2e2e959f962..243987502f7e9cecd58d274fdbeaf06c93d5c22f 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -39,16 +39,18 @@
 #include "si_dma.h"
 #include "dce_v6_0.h"
 #include "si.h"
+#include "dce_virtual.h"
 
 static const u32 tahiti_golden_registers[] =
 {
+       0x17bc, 0x00000030, 0x00000011,
        0x2684, 0x00010000, 0x00018208,
        0x260c, 0xffffffff, 0x00000000,
        0x260d, 0xf00fffff, 0x00000400,
        0x260e, 0x0002021c, 0x00020200,
        0x031e, 0x00000080, 0x00000000,
-       0x340c, 0x000300c0, 0x00800040,
-       0x360c, 0x000300c0, 0x00800040,
+       0x340c, 0x000000c0, 0x00800040,
+       0x360c, 0x000000c0, 0x00800040,
        0x16ec, 0x000000f0, 0x00000070,
        0x16f0, 0x00200000, 0x50100000,
        0x1c0c, 0x31000311, 0x00000011,
@@ -59,7 +61,7 @@ static const u32 tahiti_golden_registers[] =
        0x22c4, 0x0000ff0f, 0x00000000,
        0xa293, 0x07ffffff, 0x4e000000,
        0xa0d4, 0x3f3f3fff, 0x2a00126a,
-       0x000c, 0x000000ff, 0x0040,
+       0x000c, 0xffffffff, 0x0040,
        0x000d, 0x00000040, 0x00004040,
        0x2440, 0x07ffffff, 0x03000000,
        0x23a2, 0x01ff1f3f, 0x00000000,
@@ -72,7 +74,11 @@ static const u32 tahiti_golden_registers[] =
        0x2234, 0xffffffff, 0x000fff40,
        0x2235, 0x0000001f, 0x00000010,
        0x0504, 0x20000000, 0x20fffed8,
-       0x0570, 0x000c0fc0, 0x000c0400
+       0x0570, 0x000c0fc0, 0x000c0400,
+       0x052c, 0x0fffffff, 0xffffffff,
+       0x052d, 0x0fffffff, 0x0fffffff,
+       0x052e, 0x0fffffff, 0x0fffffff,
+       0x052f, 0x0fffffff, 0x0fffffff
 };
 
 static const u32 tahiti_golden_registers2[] =
@@ -82,12 +88,13 @@ static const u32 tahiti_golden_registers2[] =
 
 static const u32 tahiti_golden_rlc_registers[] =
 {
+       0x263e, 0xffffffff, 0x12011003,
        0x3109, 0xffffffff, 0x00601005,
        0x311f, 0xffffffff, 0x10104040,
        0x3122, 0xffffffff, 0x0100000a,
        0x30c5, 0xffffffff, 0x00000800,
        0x30c3, 0xffffffff, 0x800000f4,
-       0x3d2a, 0xffffffff, 0x00000000
+       0x3d2a, 0x00000008, 0x00000000
 };
 
 static const u32 pitcairn_golden_registers[] =
@@ -512,18 +519,18 @@ static const u32 tahiti_mgcg_cgcg_init[] =
        0x21c2, 0xffffffff, 0x00900100,
        0x311e, 0xffffffff, 0x00000080,
        0x3101, 0xffffffff, 0x0020003f,
-       0xc, 0xffffffff, 0x0000001c,
-       0xd, 0x000f0000, 0x000f0000,
-       0x583, 0xffffffff, 0x00000100,
-       0x409, 0xffffffff, 0x00000100,
-       0x40b, 0x00000101, 0x00000000,
-       0x82a, 0xffffffff, 0x00000104,
-       0x993, 0x000c0000, 0x000c0000,
-       0x992, 0x000c0000, 0x000c0000,
+       0x000c, 0xffffffff, 0x0000001c,
+       0x000d, 0x000f0000, 0x000f0000,
+       0x0583, 0xffffffff, 0x00000100,
+       0x0409, 0xffffffff, 0x00000100,
+       0x040b, 0x00000101, 0x00000000,
+       0x082a, 0xffffffff, 0x00000104,
+       0x0993, 0x000c0000, 0x000c0000,
+       0x0992, 0x000c0000, 0x000c0000,
        0x1579, 0xff000fff, 0x00000100,
        0x157a, 0x00000001, 0x00000001,
-       0xbd4, 0x00000001, 0x00000001,
-       0xc33, 0xc0000fff, 0x00000104,
+       0x0bd4, 0x00000001, 0x00000001,
+       0x0c33, 0xc0000fff, 0x00000104,
        0x3079, 0x00000001, 0x00000001,
        0x3430, 0xfffffff0, 0x00000100,
        0x3630, 0xfffffff0, 0x00000100
@@ -905,7 +912,7 @@ static void si_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
        spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
 }
 
-u32 si_pciep_rreg(struct amdgpu_device *adev, u32 reg)
+static u32 si_pciep_rreg(struct amdgpu_device *adev, u32 reg)
 {
        unsigned long flags;
        u32 r;
@@ -918,7 +925,7 @@ u32 si_pciep_rreg(struct amdgpu_device *adev, u32 reg)
        return r;
 }
 
-void si_pciep_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
+static void si_pciep_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 {
        unsigned long flags;
 
@@ -1178,6 +1185,8 @@ static int si_common_early_init(void *handle)
                        AMD_CG_SUPPORT_HDP_LS |
                        AMD_CG_SUPPORT_HDP_MGCG;
                        adev->pg_flags = 0;
+               adev->external_rev_id = (adev->rev_id == 0) ? 1 :
+                                       (adev->rev_id == 1) ? 5 : 6;
                break;
        case CHIP_PITCAIRN:
                adev->cg_flags =
@@ -1811,7 +1820,7 @@ static int si_common_set_powergating_state(void *handle,
        return 0;
 }
 
-const struct amd_ip_funcs si_common_ip_funcs = {
+static const struct amd_ip_funcs si_common_ip_funcs = {
        .name = "si_common",
        .early_init = si_common_early_init,
        .late_init = NULL,
@@ -1828,119 +1837,13 @@ const struct amd_ip_funcs si_common_ip_funcs = {
        .set_powergating_state = si_common_set_powergating_state,
 };
 
-static const struct amdgpu_ip_block_version verde_ip_blocks[] =
+static const struct amdgpu_ip_block_version si_common_ip_block =
 {
-       {
-               .type = AMD_IP_BLOCK_TYPE_COMMON,
-               .major = 1,
-               .minor = 0,
-               .rev = 0,
-               .funcs = &si_common_ip_funcs,
-       },
-       {
-               .type = AMD_IP_BLOCK_TYPE_GMC,
-               .major = 6,
-               .minor = 0,
-               .rev = 0,
-               .funcs = &gmc_v6_0_ip_funcs,
-       },
-       {
-               .type = AMD_IP_BLOCK_TYPE_IH,
-               .major = 1,
-               .minor = 0,
-               .rev = 0,
-               .funcs = &si_ih_ip_funcs,
-       },
-       {
-               .type = AMD_IP_BLOCK_TYPE_SMC,
-               .major = 6,
-               .minor = 0,
-               .rev = 0,
-               .funcs = &amdgpu_pp_ip_funcs,
-       },
-       {
-               .type = AMD_IP_BLOCK_TYPE_DCE,
-               .major = 6,
-               .minor = 0,
-               .rev = 0,
-               .funcs = &dce_v6_0_ip_funcs,
-       },
-       {
-               .type = AMD_IP_BLOCK_TYPE_GFX,
-               .major = 6,
-               .minor = 0,
-               .rev = 0,
-               .funcs = &gfx_v6_0_ip_funcs,
-       },
-       {
-               .type = AMD_IP_BLOCK_TYPE_SDMA,
-               .major = 1,
-               .minor = 0,
-               .rev = 0,
-               .funcs = &si_dma_ip_funcs,
-       },
-/*     {
-               .type = AMD_IP_BLOCK_TYPE_UVD,
-               .major = 3,
-               .minor = 1,
-               .rev = 0,
-               .funcs = &si_null_ip_funcs,
-       },
-       {
-               .type = AMD_IP_BLOCK_TYPE_VCE,
-               .major = 1,
-               .minor = 0,
-               .rev = 0,
-               .funcs = &si_null_ip_funcs,
-       },
-       */
-};
-
-
-static const struct amdgpu_ip_block_version hainan_ip_blocks[] =
-{
-       {
-               .type = AMD_IP_BLOCK_TYPE_COMMON,
-               .major = 1,
-               .minor = 0,
-               .rev = 0,
-               .funcs = &si_common_ip_funcs,
-       },
-       {
-               .type = AMD_IP_BLOCK_TYPE_GMC,
-               .major = 6,
-               .minor = 0,
-               .rev = 0,
-               .funcs = &gmc_v6_0_ip_funcs,
-       },
-       {
-               .type = AMD_IP_BLOCK_TYPE_IH,
-               .major = 1,
-               .minor = 0,
-               .rev = 0,
-               .funcs = &si_ih_ip_funcs,
-       },
-       {
-               .type = AMD_IP_BLOCK_TYPE_SMC,
-               .major = 6,
-               .minor = 0,
-               .rev = 0,
-               .funcs = &amdgpu_pp_ip_funcs,
-       },
-       {
-               .type = AMD_IP_BLOCK_TYPE_GFX,
-               .major = 6,
-               .minor = 0,
-               .rev = 0,
-               .funcs = &gfx_v6_0_ip_funcs,
-       },
-       {
-               .type = AMD_IP_BLOCK_TYPE_SDMA,
-               .major = 1,
-               .minor = 0,
-               .rev = 0,
-               .funcs = &si_dma_ip_funcs,
-       },
+       .type = AMD_IP_BLOCK_TYPE_COMMON,
+       .major = 1,
+       .minor = 0,
+       .rev = 0,
+       .funcs = &si_common_ip_funcs,
 };
 
 int si_set_ip_blocks(struct amdgpu_device *adev)
@@ -1949,13 +1852,42 @@ int si_set_ip_blocks(struct amdgpu_device *adev)
        case CHIP_VERDE:
        case CHIP_TAHITI:
        case CHIP_PITCAIRN:
+               amdgpu_ip_block_add(adev, &si_common_ip_block);
+               amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block);
+               amdgpu_ip_block_add(adev, &si_ih_ip_block);
+               amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
+               if (adev->enable_virtual_display)
+                       amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
+               else
+                       amdgpu_ip_block_add(adev, &dce_v6_0_ip_block);
+               amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block);
+               amdgpu_ip_block_add(adev, &si_dma_ip_block);
+               /* amdgpu_ip_block_add(adev, &uvd_v3_1_ip_block); */
+               /* amdgpu_ip_block_add(adev, &vce_v1_0_ip_block); */
+               break;
        case CHIP_OLAND:
-               adev->ip_blocks = verde_ip_blocks;
-               adev->num_ip_blocks = ARRAY_SIZE(verde_ip_blocks);
+               amdgpu_ip_block_add(adev, &si_common_ip_block);
+               amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block);
+               amdgpu_ip_block_add(adev, &si_ih_ip_block);
+               amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
+               if (adev->enable_virtual_display)
+                       amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
+               else
+                       amdgpu_ip_block_add(adev, &dce_v6_4_ip_block);
+               amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block);
+               amdgpu_ip_block_add(adev, &si_dma_ip_block);
+               /* amdgpu_ip_block_add(adev, &uvd_v3_1_ip_block); */
+               /* amdgpu_ip_block_add(adev, &vce_v1_0_ip_block); */
                break;
        case CHIP_HAINAN:
-               adev->ip_blocks = hainan_ip_blocks;
-               adev->num_ip_blocks = ARRAY_SIZE(hainan_ip_blocks);
+               amdgpu_ip_block_add(adev, &si_common_ip_block);
+               amdgpu_ip_block_add(adev, &gmc_v6_0_ip_block);
+               amdgpu_ip_block_add(adev, &si_ih_ip_block);
+               amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
+               if (adev->enable_virtual_display)
+                       amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
+               amdgpu_ip_block_add(adev, &gfx_v6_0_ip_block);
+               amdgpu_ip_block_add(adev, &si_dma_ip_block);
                break;
        default:
                BUG();
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