Merge tag 'kvm-s390-master-4.10-1' of git://git.kernel.org/pub/scm/linux/kernel/git...

[karo-tx-linux.git] / drivers / gpu / drm / amd / amdgpu / vi.c

diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 9f771f4ffcb71bf1267ff3aae9c5853fb944e149..c2ac54f1134179457db3823eb64161817ee8f5b3 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -88,6 +88,7 @@ MODULE_FIRMWARE("amdgpu/polaris10_smc.bin");
 MODULE_FIRMWARE("amdgpu/polaris10_smc_sk.bin");
 MODULE_FIRMWARE("amdgpu/polaris11_smc.bin");
 MODULE_FIRMWARE("amdgpu/polaris11_smc_sk.bin");
+MODULE_FIRMWARE("amdgpu/polaris12_smc.bin");
 
 /*
  * Indirect registers accessor
@@ -312,6 +313,7 @@ static void vi_init_golden_registers(struct amdgpu_device *adev)
                break;
        case CHIP_POLARIS11:
        case CHIP_POLARIS10:
+       case CHIP_POLARIS12:
        default:
                break;
        }
@@ -671,6 +673,7 @@ static int vi_read_register(struct amdgpu_device *adev, u32 se_num,
        case CHIP_TONGA:
        case CHIP_POLARIS11:
        case CHIP_POLARIS10:
+       case CHIP_POLARIS12:
        case CHIP_CARRIZO:
        case CHIP_STONEY:
                asic_register_table = cz_allowed_read_registers;
@@ -932,22 +935,73 @@ static int vi_common_early_init(void *handle)
                adev->external_rev_id = adev->rev_id + 0x3c;
                break;
        case CHIP_TONGA:
-               adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG;
-               adev->pg_flags = AMD_PG_SUPPORT_UVD;
+               adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
+                       AMD_CG_SUPPORT_GFX_CGCG |
+                       AMD_CG_SUPPORT_GFX_CGLS |
+                       AMD_CG_SUPPORT_SDMA_MGCG |
+                       AMD_CG_SUPPORT_SDMA_LS |
+                       AMD_CG_SUPPORT_BIF_LS |
+                       AMD_CG_SUPPORT_HDP_MGCG |
+                       AMD_CG_SUPPORT_HDP_LS |
+                       AMD_CG_SUPPORT_ROM_MGCG |
+                       AMD_CG_SUPPORT_MC_MGCG |
+                       AMD_CG_SUPPORT_MC_LS |
+                       AMD_CG_SUPPORT_DRM_LS |
+                       AMD_CG_SUPPORT_UVD_MGCG;
+               adev->pg_flags = 0;
                adev->external_rev_id = adev->rev_id + 0x14;
                break;
        case CHIP_POLARIS11:
-               adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
+               adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
+                       AMD_CG_SUPPORT_GFX_RLC_LS |
+                       AMD_CG_SUPPORT_GFX_CP_LS |
+                       AMD_CG_SUPPORT_GFX_CGCG |
+                       AMD_CG_SUPPORT_GFX_CGLS |
+                       AMD_CG_SUPPORT_GFX_3D_CGCG |
+                       AMD_CG_SUPPORT_GFX_3D_CGLS |
+                       AMD_CG_SUPPORT_SDMA_MGCG |
+                       AMD_CG_SUPPORT_SDMA_LS |
+                       AMD_CG_SUPPORT_BIF_MGCG |
+                       AMD_CG_SUPPORT_BIF_LS |
+                       AMD_CG_SUPPORT_HDP_MGCG |
+                       AMD_CG_SUPPORT_HDP_LS |
+                       AMD_CG_SUPPORT_ROM_MGCG |
+                       AMD_CG_SUPPORT_MC_MGCG |
+                       AMD_CG_SUPPORT_MC_LS |
+                       AMD_CG_SUPPORT_DRM_LS |
+                       AMD_CG_SUPPORT_UVD_MGCG |
                        AMD_CG_SUPPORT_VCE_MGCG;
                adev->pg_flags = 0;
                adev->external_rev_id = adev->rev_id + 0x5A;
                break;
        case CHIP_POLARIS10:
-               adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
+               adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
+                       AMD_CG_SUPPORT_GFX_RLC_LS |
+                       AMD_CG_SUPPORT_GFX_CP_LS |
+                       AMD_CG_SUPPORT_GFX_CGCG |
+                       AMD_CG_SUPPORT_GFX_CGLS |
+                       AMD_CG_SUPPORT_GFX_3D_CGCG |
+                       AMD_CG_SUPPORT_GFX_3D_CGLS |
+                       AMD_CG_SUPPORT_SDMA_MGCG |
+                       AMD_CG_SUPPORT_SDMA_LS |
+                       AMD_CG_SUPPORT_BIF_MGCG |
+                       AMD_CG_SUPPORT_BIF_LS |
+                       AMD_CG_SUPPORT_HDP_MGCG |
+                       AMD_CG_SUPPORT_HDP_LS |
+                       AMD_CG_SUPPORT_ROM_MGCG |
+                       AMD_CG_SUPPORT_MC_MGCG |
+                       AMD_CG_SUPPORT_MC_LS |
+                       AMD_CG_SUPPORT_DRM_LS |
+                       AMD_CG_SUPPORT_UVD_MGCG |
                        AMD_CG_SUPPORT_VCE_MGCG;
                adev->pg_flags = 0;
                adev->external_rev_id = adev->rev_id + 0x50;
                break;
+       case CHIP_POLARIS12:
+               adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG;
+               adev->pg_flags = 0;
+               adev->external_rev_id = adev->rev_id + 0x64;
+               break;
        case CHIP_CARRIZO:
                adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
                        AMD_CG_SUPPORT_GFX_MGCG |
@@ -971,6 +1025,7 @@ static int vi_common_early_init(void *handle)
                        adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
                                AMD_PG_SUPPORT_GFX_SMG |
                                AMD_PG_SUPPORT_GFX_PIPELINE |
+                               AMD_PG_SUPPORT_CP |
                                AMD_PG_SUPPORT_UVD |
                                AMD_PG_SUPPORT_VCE;
                }
@@ -996,6 +1051,7 @@ static int vi_common_early_init(void *handle)
                adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
                        AMD_PG_SUPPORT_GFX_SMG |
                        AMD_PG_SUPPORT_GFX_PIPELINE |
+                       AMD_PG_SUPPORT_CP |
                        AMD_PG_SUPPORT_UVD |
                        AMD_PG_SUPPORT_VCE;
                adev->external_rev_id = adev->rev_id + 0x61;
@@ -1155,57 +1211,118 @@ static void vi_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
 static int vi_common_set_clockgating_state_by_smu(void *handle,
                                           enum amd_clockgating_state state)
 {
-       uint32_t msg_id, pp_state;
+       uint32_t msg_id, pp_state = 0;
+       uint32_t pp_support_state = 0;
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
        void *pp_handle = adev->powerplay.pp_handle;
 
-       if (state == AMD_CG_STATE_UNGATE)
-               pp_state = 0;
-       else
-               pp_state = PP_STATE_CG | PP_STATE_LS;
-
-       msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
-                      PP_BLOCK_SYS_MC,
-                      PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
-                      pp_state);
-       amd_set_clockgating_by_smu(pp_handle, msg_id);
-
-       msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
-                      PP_BLOCK_SYS_SDMA,
-                      PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
-                      pp_state);
-       amd_set_clockgating_by_smu(pp_handle, msg_id);
-
-       msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
-                      PP_BLOCK_SYS_HDP,
-                      PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
-                      pp_state);
-       amd_set_clockgating_by_smu(pp_handle, msg_id);
-
-       msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
-                      PP_BLOCK_SYS_BIF,
-                      PP_STATE_SUPPORT_LS,
-                      pp_state);
-       amd_set_clockgating_by_smu(pp_handle, msg_id);
-
-       msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
-                      PP_BLOCK_SYS_BIF,
-                      PP_STATE_SUPPORT_CG,
-                      pp_state);
-       amd_set_clockgating_by_smu(pp_handle, msg_id);
-
-       msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
-                      PP_BLOCK_SYS_DRM,
-                      PP_STATE_SUPPORT_LS,
-                      pp_state);
-       amd_set_clockgating_by_smu(pp_handle, msg_id);
-
-       msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
-                      PP_BLOCK_SYS_ROM,
-                      PP_STATE_SUPPORT_CG,
-                      pp_state);
-       amd_set_clockgating_by_smu(pp_handle, msg_id);
+       if (adev->cg_flags & (AMD_CG_SUPPORT_MC_LS | AMD_CG_SUPPORT_MC_MGCG)) {
+               if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) {
+                       pp_support_state = AMD_CG_SUPPORT_MC_LS;
+                       pp_state = PP_STATE_LS;
+               }
+               if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG) {
+                       pp_support_state |= AMD_CG_SUPPORT_MC_MGCG;
+                       pp_state |= PP_STATE_CG;
+               }
+               if (state == AMD_CG_STATE_UNGATE)
+                       pp_state = 0;
+               msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
+                              PP_BLOCK_SYS_MC,
+                              pp_support_state,
+                              pp_state);
+               amd_set_clockgating_by_smu(pp_handle, msg_id);
+       }
 
+       if (adev->cg_flags & (AMD_CG_SUPPORT_SDMA_LS | AMD_CG_SUPPORT_SDMA_MGCG)) {
+               if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS) {
+                       pp_support_state = AMD_CG_SUPPORT_SDMA_LS;
+                       pp_state = PP_STATE_LS;
+               }
+               if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG) {
+                       pp_support_state |= AMD_CG_SUPPORT_SDMA_MGCG;
+                       pp_state |= PP_STATE_CG;
+               }
+               if (state == AMD_CG_STATE_UNGATE)
+                       pp_state = 0;
+               msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
+                              PP_BLOCK_SYS_SDMA,
+                              pp_support_state,
+                              pp_state);
+               amd_set_clockgating_by_smu(pp_handle, msg_id);
+       }
+
+       if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_MGCG)) {
+               if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
+                       pp_support_state = AMD_CG_SUPPORT_HDP_LS;
+                       pp_state = PP_STATE_LS;
+               }
+               if (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG) {
+                       pp_support_state |= AMD_CG_SUPPORT_HDP_MGCG;
+                       pp_state |= PP_STATE_CG;
+               }
+               if (state == AMD_CG_STATE_UNGATE)
+                       pp_state = 0;
+               msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
+                              PP_BLOCK_SYS_HDP,
+                              pp_support_state,
+                              pp_state);
+               amd_set_clockgating_by_smu(pp_handle, msg_id);
+       }
+
+
+       if (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS) {
+               if (state == AMD_CG_STATE_UNGATE)
+                       pp_state = 0;
+               else
+                       pp_state = PP_STATE_LS;
+
+               msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
+                              PP_BLOCK_SYS_BIF,
+                              PP_STATE_SUPPORT_LS,
+                               pp_state);
+               amd_set_clockgating_by_smu(pp_handle, msg_id);
+       }
+       if (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG) {
+               if (state == AMD_CG_STATE_UNGATE)
+                       pp_state = 0;
+               else
+                       pp_state = PP_STATE_CG;
+
+               msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
+                              PP_BLOCK_SYS_BIF,
+                              PP_STATE_SUPPORT_CG,
+                              pp_state);
+               amd_set_clockgating_by_smu(pp_handle, msg_id);
+       }
+
+       if (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS) {
+
+               if (state == AMD_CG_STATE_UNGATE)
+                       pp_state = 0;
+               else
+                       pp_state = PP_STATE_LS;
+
+               msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
+                              PP_BLOCK_SYS_DRM,
+                              PP_STATE_SUPPORT_LS,
+                              pp_state);
+               amd_set_clockgating_by_smu(pp_handle, msg_id);
+       }
+
+       if (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG) {
+
+               if (state == AMD_CG_STATE_UNGATE)
+                       pp_state = 0;
+               else
+                       pp_state = PP_STATE_CG;
+
+               msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
+                              PP_BLOCK_SYS_ROM,
+                              PP_STATE_SUPPORT_CG,
+                              pp_state);
+               amd_set_clockgating_by_smu(pp_handle, msg_id);
+       }
        return 0;
 }
 
@@ -1237,6 +1354,7 @@ static int vi_common_set_clockgating_state(void *handle,
        case CHIP_TONGA:
        case CHIP_POLARIS10:
        case CHIP_POLARIS11:
+       case CHIP_POLARIS12:
                vi_common_set_clockgating_state_by_smu(adev, state);
        default:
                break;
@@ -1320,6 +1438,7 @@ int vi_set_ip_blocks(struct amdgpu_device *adev)
                break;
        case CHIP_POLARIS11:
        case CHIP_POLARIS10:
+       case CHIP_POLARIS12:
                amdgpu_ip_block_add(adev, &vi_common_ip_block);
                amdgpu_ip_block_add(adev, &gmc_v8_1_ip_block);
                amdgpu_ip_block_add(adev, &tonga_ih_ip_block);