intel_lr_context_reset(dev, ctx);
}
- for (i = 0; i < I915_NUM_RINGS; i++) {
+ for (i = 0; i < I915_NUM_ENGINES; i++) {
struct intel_engine_cs *engine = &dev_priv->engine[i];
if (engine->last_context) {
i915_gem_object_ggtt_unpin(dctx->legacy_hw_ctx.rcs_state);
}
- for (i = I915_NUM_RINGS; --i >= 0;) {
+ for (i = I915_NUM_ENGINES; --i >= 0;) {
struct intel_engine_cs *engine = &dev_priv->engine[i];
if (engine->last_context) {
intel_ring_emit(engine,
MI_LOAD_REGISTER_IMM(num_rings));
- for_each_ring(signaller, to_i915(engine->dev), i) {
+ for_each_engine(signaller, to_i915(engine->dev), i) {
if (signaller == engine)
continue;
intel_ring_emit(engine,
MI_LOAD_REGISTER_IMM(num_rings));
- for_each_ring(signaller, to_i915(engine->dev), i) {
+ for_each_engine(signaller, to_i915(engine->dev), i) {
if (signaller == engine)
continue;
return false;
if (to->ppgtt && from == to &&
- !(intel_ring_flag(engine) & to->ppgtt->pd_dirty_rings))
+ !(intel_engine_flag(engine) & to->ppgtt->pd_dirty_rings))
return true;
return false;
goto unpin_out;
/* Doing a PD load always reloads the page dirs */
- to->ppgtt->pd_dirty_rings &= ~intel_ring_flag(engine);
+ to->ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine);
}
if (engine != &dev_priv->engine[RCS]) {
* space. This means we must enforce that a page table load
* occur when this occurs. */
} else if (to->ppgtt &&
- (intel_ring_flag(engine) & to->ppgtt->pd_dirty_rings)) {
+ (intel_engine_flag(engine) & to->ppgtt->pd_dirty_rings)) {
hw_flags |= MI_FORCE_RESTORE;
- to->ppgtt->pd_dirty_rings &= ~intel_ring_flag(engine);
+ to->ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine);
}
/* We should never emit switch_mm more than once */