drm/i915: Rearrange i915_wait_request() accounting with callers

[karo-tx-linux.git] / drivers / gpu / drm / i915 / i915_gem_fence.c

diff --git a/drivers/gpu/drm/i915/i915_gem_fence.c b/drivers/gpu/drm/i915/i915_gem_fence.c
index 8df1fa7234e8e031e9c61da4608c5c4b7610476b..3c5a8082cac3bfc21a9ef3cc2bf779c9c979717f 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_fence.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence.c
@@ -290,6 +290,8 @@ i915_vma_put_fence(struct i915_vma *vma)
 {
        struct drm_i915_fence_reg *fence = vma->fence;
 
+       assert_rpm_wakelock_held(to_i915(vma->vm->dev));
+
        if (!fence)
                return 0;
 
@@ -341,6 +343,11 @@ i915_vma_get_fence(struct i915_vma *vma)
        struct drm_i915_fence_reg *fence;
        struct i915_vma *set = i915_gem_object_is_tiled(vma->obj) ? vma : NULL;
 
+       /* Note that we revoke fences on runtime suspend. Therefore the user
+        * must keep the device awake whilst using the fence.
+        */
+       assert_rpm_wakelock_held(to_i915(vma->vm->dev));
+
        /* Just update our place in the LRU if our fence is getting reused. */
        if (vma->fence) {
                fence = vma->fence;
@@ -364,7 +371,8 @@ i915_vma_get_fence(struct i915_vma *vma)
  * @dev: DRM device
  *
  * Restore the hw fence state to match the software tracking again, to be called
- * after a gpu reset and on resume.
+ * after a gpu reset and on resume. Note that on runtime suspend we only cancel
+ * the fences, to be reacquired by the user later.
  */
 void i915_gem_restore_fences(struct drm_device *dev)
 {
@@ -379,10 +387,17 @@ void i915_gem_restore_fences(struct drm_device *dev)
                 * Commit delayed tiling changes if we have an object still
                 * attached to the fence, otherwise just clear the fence.
                 */
-               if (vma && !i915_gem_object_is_tiled(vma->obj))
+               if (vma && !i915_gem_object_is_tiled(vma->obj)) {
+                       GEM_BUG_ON(!reg->dirty);
+                       GEM_BUG_ON(!list_empty(&vma->obj->userfault_link));
+
+                       list_move(&reg->link, &dev_priv->mm.fence_list);
+                       vma->fence = NULL;
                        vma = NULL;
+               }
 
-               fence_update(reg, vma);
+               fence_write(reg, vma);
+               reg->vma = vma;
        }
 }
 
@@ -448,7 +463,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
        uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
        uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
 
-       if (INTEL_INFO(dev)->gen >= 8 || IS_VALLEYVIEW(dev)) {
+       if (INTEL_GEN(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv)) {
                /*
                 * On BDW+, swizzling is not used. We leave the CPU memory
                 * controller in charge of optimizing memory accesses without
@@ -487,19 +502,20 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
                                swizzle_y = I915_BIT_6_SWIZZLE_NONE;
                        }
                }
-       } else if (IS_GEN5(dev)) {
+       } else if (IS_GEN5(dev_priv)) {
                /* On Ironlake whatever DRAM config, GPU always do
                 * same swizzling setup.
                 */
                swizzle_x = I915_BIT_6_SWIZZLE_9_10;
                swizzle_y = I915_BIT_6_SWIZZLE_9;
-       } else if (IS_GEN2(dev)) {
+       } else if (IS_GEN2(dev_priv)) {
                /* As far as we know, the 865 doesn't have these bit 6
                 * swizzling issues.
                 */
                swizzle_x = I915_BIT_6_SWIZZLE_NONE;
                swizzle_y = I915_BIT_6_SWIZZLE_NONE;
-       } else if (IS_MOBILE(dev) || (IS_GEN3(dev) && !IS_G33(dev))) {
+       } else if (IS_MOBILE(dev_priv) || (IS_GEN3(dev_priv) &&
+                  !IS_G33(dev_priv))) {
                uint32_t dcc;
 
                /* On 9xx chipsets, channel interleave by the CPU is
@@ -537,7 +553,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
                }
 
                /* check for L-shaped memory aka modified enhanced addressing */
-               if (IS_GEN4(dev) &&
+               if (IS_GEN4(dev_priv) &&
                    !(I915_READ(DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) {
                        swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
                        swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;