Merge branch 'v4l_for_linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab...

[karo-tx-linux.git] / drivers / gpu / drm / i915 / intel_i2c.c

diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 82d04c5899d27d9942c4fa47a3222f21d3e97993..d3b903bce7c5b3a25845c570aaf21f064d416224 100644 (file)
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -259,7 +259,7 @@ gmbus_xfer(struct i2c_adapter *adapter,
                                if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
                                        goto timeout;
                                if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
-                                       return 0;
+                                       goto clear_err;
 
                                val = I915_READ(GMBUS3 + reg_offset);
                                do {
@@ -287,7 +287,7 @@ gmbus_xfer(struct i2c_adapter *adapter,
                                if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
                                        goto timeout;
                                if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
-                                       return 0;
+                                       goto clear_err;
 
                                val = loop = 0;
                                do {
@@ -302,14 +302,31 @@ gmbus_xfer(struct i2c_adapter *adapter,
                if (i + 1 < num && wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50))
                        goto timeout;
                if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
-                       return 0;
+                       goto clear_err;
        }
 
-       return num;
+       goto done;
+
+clear_err:
+       /* Toggle the Software Clear Interrupt bit. This has the effect
+        * of resetting the GMBUS controller and so clearing the
+        * BUS_ERROR raised by the slave's NAK.
+        */
+       I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
+       I915_WRITE(GMBUS1 + reg_offset, 0);
+
+done:
+       /* Mark the GMBUS interface as disabled. We will re-enable it at the
+        * start of the next xfer, till then let it sleep.
+        */
+       I915_WRITE(GMBUS0 + reg_offset, 0);
+       return i;
 
 timeout:
        DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n",
                 bus->reg0 & 0xff, bus->adapter.name);
+       I915_WRITE(GMBUS0 + reg_offset, 0);
+
        /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
        bus->force_bit = intel_gpio_create(dev_priv, bus->reg0 & 0xff);
        if (!bus->force_bit)