drm/nouveau/device: include the official chipset names

[karo-tx-linux.git] / drivers / gpu / drm / nouveau / nouveau_compat.h

diff --git a/drivers/gpu/drm/nouveau/nouveau_compat.h b/drivers/gpu/drm/nouveau/nouveau_compat.h
index 7ffad0a7a30143902eab9c58eee9ca58a08fdc15..9f42d1d0f868ad9c5b4dc3c8e6fd14524b4092d0 100644 (file)
--- a/drivers/gpu/drm/nouveau/nouveau_compat.h
+++ b/drivers/gpu/drm/nouveau/nouveau_compat.h
@@ -51,4 +51,91 @@ struct dcb_output;
 void nouveau_bios_run_init_table(struct drm_device *, u16, struct dcb_output *, int);
 void nouveau_bios_init_exec(struct drm_device *, u16);
 
+void nv_intr(struct drm_device *);
+
+bool nouveau_wait_eq(struct drm_device *, uint64_t timeout,
+                           uint32_t reg, uint32_t mask, uint32_t val);
+bool nouveau_wait_ne(struct drm_device *, uint64_t timeout,
+                           uint32_t reg, uint32_t mask, uint32_t val);
+bool nouveau_wait_cb(struct drm_device *, u64 timeout,
+                           bool (*cond)(void *), void *);
+
+u64 nv_timer_read(struct drm_device *);
+
+int  nvfb_tile_nr(struct drm_device *);
+void nvfb_tile_init(struct drm_device *, int, u32, u32, u32, u32);
+void nvfb_tile_fini(struct drm_device *, int);
+void nvfb_tile_prog(struct drm_device *, int);
+
+struct nouveau_fb_tile *nvfb_tile(struct drm_device *, int);
+
+struct nouveau_mem;
+int nvfb_vram_get(struct drm_device *dev, u64 size, u32 align, u32 ncmin,
+                 u32 memtype, struct nouveau_mem **pmem);
+void nvfb_vram_put(struct drm_device *dev, struct nouveau_mem **pmem);
+bool nvfb_flags_valid(struct drm_device *dev, u32);
+
+u64 nvfb_vram_sys_base(struct drm_device *);
+u64 nvfb_vram_size(struct drm_device *);
+int nvfb_vram_type(struct drm_device *);
+int nvfb_vram_rank_B(struct drm_device *);
+
+void nv50_fb_vm_trap(struct drm_device *, int);
+
+struct nouveau_gpuobj *nvimem_ramro(struct drm_device *);
+struct nouveau_gpuobj *nvimem_ramfc(struct drm_device *);
+
+int _nouveau_gpuobj_new(struct drm_device *dev, struct nouveau_gpuobj *par,
+                       int size, int align, u32 flags,
+                       struct nouveau_gpuobj **pboj);
+
+u32 nv_ri32(struct drm_device *, u32);
+void nv_wi32(struct drm_device *, u32, u32);
+u32 nvimem_reserved(struct drm_device *);
+
+void nvimem_flush(struct drm_device *);
+
+void _nv50_vm_flush_engine(struct drm_device *dev, int engine);
+
+int _nouveau_vm_new(struct drm_device *, u64 offset, u64 length,
+                   u64 mm_offset, struct nouveau_vm **);
+
+struct nouveau_vma;
+int nouveau_gpuobj_map_bar(struct nouveau_gpuobj *, u32, struct nouveau_vma *);
+
+int
+nvbar_map(struct drm_device *dev, struct nouveau_mem *mem, u32 flags,
+         struct nouveau_vma *vma);
+void
+nvbar_unmap(struct drm_device *dev, struct nouveau_vma *vma);
+
+struct nouveau_vm *
+nv04vm_ref(struct drm_device *dev);
+
+struct nouveau_gpuobj *
+nv04vm_refdma(struct drm_device *dev);
+
+void
+nvvm_engref(struct nouveau_vm *, int, int);
+
+int
+nvvm_spg_shift(struct nouveau_vm *);
+
+int
+nvvm_lpg_shift(struct nouveau_vm *);
+
+u32
+nv50_display_active_crtcs(struct drm_device *dev);
+
+u64 nvgpuobj_addr(struct nouveau_object *object);
+
+struct drm_device *
+nouveau_drv(void *drm);
+
+struct nouveau_channel *
+nvdrm_channel(struct drm_device *dev);
+
+struct mutex *
+nvchan_mutex(struct nouveau_channel *chan);
+
 #endif