Merge branch 'kbuild' of git://git.kernel.org/pub/scm/linux/kernel/git/mmarek/kbuild

[karo-tx-linux.git] / drivers / gpu / drm / nouveau / nv40_graph.c

diff --git a/drivers/gpu/drm/nouveau/nv40_graph.c b/drivers/gpu/drm/nouveau/nv40_graph.c
index ba14a93d8afa5f07ed43474d9a560a04415b5964..aa9e2df64a26d5b28ee62825453ebdcbd8128cc0 100644 (file)
--- a/drivers/gpu/drm/nouveau/nv40_graph.c
+++ b/drivers/gpu/drm/nouveau/nv40_graph.c
@@ -27,7 +27,7 @@
 #include "drmP.h"
 #include "drm.h"
 #include "nouveau_drv.h"
-#include "nouveau_grctx.h"
+#include "nouveau_fifo.h"
 #include "nouveau_ramht.h"
 
 struct nv40_graph_engine {
@@ -42,7 +42,6 @@ nv40_graph_context_new(struct nouveau_channel *chan, int engine)
        struct drm_device *dev = chan->dev;
        struct drm_nouveau_private *dev_priv = dev->dev_private;
        struct nouveau_gpuobj *grctx = NULL;
-       struct nouveau_grctx ctx = {};
        unsigned long flags;
        int ret;
 
@@ -52,11 +51,7 @@ nv40_graph_context_new(struct nouveau_channel *chan, int engine)
                return ret;
 
        /* Initialise default context values */
-       ctx.dev = chan->dev;
-       ctx.mode = NOUVEAU_GRCTX_VALS;
-       ctx.data = grctx;
-       nv40_grctx_init(&ctx);
-
+       nv40_grctx_fill(dev, grctx);
        nv_wo32(grctx, 0, grctx->vinst);
 
        /* init grctx pointer in ramfc, and on PFIFO if channel is
@@ -184,8 +179,7 @@ nv40_graph_init(struct drm_device *dev, int engine)
        struct nv40_graph_engine *pgraph = nv_engine(dev, engine);
        struct drm_nouveau_private *dev_priv = dev->dev_private;
        struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
-       struct nouveau_grctx ctx = {};
-       uint32_t vramsz, *cp;
+       uint32_t vramsz;
        int i, j;
 
        nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) &
@@ -193,22 +187,8 @@ nv40_graph_init(struct drm_device *dev, int engine)
        nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
                         NV_PMC_ENABLE_PGRAPH);
 
-       cp = kmalloc(sizeof(*cp) * 256, GFP_KERNEL);
-       if (!cp)
-               return -ENOMEM;
-
-       ctx.dev = dev;
-       ctx.mode = NOUVEAU_GRCTX_PROG;
-       ctx.data = cp;
-       ctx.ctxprog_max = 256;
-       nv40_grctx_init(&ctx);
-       pgraph->grctx_size = ctx.ctxvals_pos * 4;
-
-       nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
-       for (i = 0; i < ctx.ctxprog_len; i++)
-               nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);
-
-       kfree(cp);
+       /* generate and upload context program */
+       nv40_grctx_init(dev, &pgraph->grctx_size);
 
        /* No context present currently */
        nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
@@ -366,13 +346,14 @@ nv40_graph_fini(struct drm_device *dev, int engine, bool suspend)
 static int
 nv40_graph_isr_chid(struct drm_device *dev, u32 inst)
 {
+       struct nouveau_fifo_priv *pfifo = nv_engine(dev, NVOBJ_ENGINE_FIFO);
        struct drm_nouveau_private *dev_priv = dev->dev_private;
        struct nouveau_gpuobj *grctx;
        unsigned long flags;
        int i;
 
        spin_lock_irqsave(&dev_priv->channels.lock, flags);
-       for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
+       for (i = 0; i < pfifo->channels; i++) {
                if (!dev_priv->channels.ptr[i])
                        continue;
                grctx = dev_priv->channels.ptr[i]->engctx[NVOBJ_ENGINE_GR];
@@ -460,7 +441,6 @@ nv40_graph_create(struct drm_device *dev)
        NVOBJ_ENGINE_ADD(dev, GR, &pgraph->base);
        nouveau_irq_register(dev, 12, nv40_graph_isr);
 
-       NVOBJ_CLASS(dev, 0x506e, SW); /* nvsw */
        NVOBJ_CLASS(dev, 0x0030, GR); /* null */
        NVOBJ_CLASS(dev, 0x0039, GR); /* m2mf */
        NVOBJ_CLASS(dev, 0x004a, GR); /* gdirect */
@@ -483,8 +463,5 @@ nv40_graph_create(struct drm_device *dev)
        else
                NVOBJ_CLASS(dev, 0x4097, GR);
 
-       /* nvsw */
-       NVOBJ_CLASS(dev, 0x506e, SW);
-       NVOBJ_MTHD (dev, 0x506e, 0x0500, nv04_graph_mthd_page_flip);
        return 0;
 }