struct gpio_desc *enable_gpio;
u32 bus_fmt_override;
+ u32 quirks;
+};
+
+enum {
+ PANEL_QUIRK_PIXDATA_NEGEDGE = BIT(0),
+ PANEL_QUIRK_PIXDATA_POSEDGE = BIT(1),
};
#define SP_DISPLAY_MODE(freq, ha, hfp, hs, hbp, va, vfp, vs, vbp, vr, flgs) { \
return container_of(panel, struct panel_simple, base);
}
+static inline void panel_simple_apply_quirks(struct panel_simple *panel,
+ struct drm_display_info *info)
+{
+ if (panel->quirks & PANEL_QUIRK_PIXDATA_NEGEDGE)
+ info->bus_flags |= DRM_BUS_FLAG_PIXDATA_NEGEDGE;
+ if (panel->quirks & PANEL_QUIRK_PIXDATA_POSEDGE)
+ info->bus_flags |= DRM_BUS_FLAG_PIXDATA_POSEDGE;
+}
+
static int panel_simple_get_fixed_modes(struct panel_simple *panel)
{
struct drm_connector *connector = panel->base.connector;
drm_display_info_set_bus_formats(&connector->display_info,
&panel->desc->bus_format, 1);
connector->display_info.bus_flags = panel->desc->bus_flags;
+ if (panel->quirks)
+ panel_simple_apply_quirks(panel, &connector->display_info);
return num;
}
struct panel_simple *p)
{
const char *bus_fmt;
+ u32 clkpol;
if (of_property_read_string(dev->of_node, "bus-format-override",
&bus_fmt) == 0) {
bus_fmt);
return p->bus_fmt_override ? 0 : -EINVAL;
}
+
+ if (of_property_read_u32(dev->of_node, "pixelclk-active",
+ &clkpol) == 0) {
+ if (clkpol & ~1) {
+ dev_err(dev,
+ "Invalid value for pixelclk-active: '%u' (should be <0> or <1>)\n",
+ clkpol);
+ return -EINVAL;
+ }
+ p->quirks |= clkpol ? PANEL_QUIRK_PIXDATA_POSEDGE :
+ PANEL_QUIRK_PIXDATA_NEGEDGE;
+ }
return 0;
}
},
};
+static const struct drm_display_mode edt_et0350g0dh6_mode =
+ SP_DISPLAY_MODE(6500, 320, 20, 0, 68, 240, 4, 0, 18, 60,
+ DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
+
+static const struct panel_desc edt_et0350g0dh6 = {
+ .modes = &edt_et0350g0dh6_mode,
+ .num_modes = 1,
+ .bpc = 6,
+ .size = {
+ .width = 70,
+ .height = 53,
+ },
+ .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
+ .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_NEGEDGE,
+};
+
static const struct drm_display_mode edt_et057090dhu_mode =
SP_DISPLAY_MODE(25175, 640, 16, 30, 114, 480, 10, 3, 32, 60,
DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC);
}, {
.compatible = "chunghwa,claa101wb01",
.data = &chunghwa_claa101wb01
+ }, {
+ .compatible = "edt,et0350g0dh6",
+ .data = &edt_et0350g0dh6,
}, {
.compatible = "edt,et057090dhu",
.data = &edt_et057090dhu,