drm/radeon: disable compute rings on cayman for now

[mv-sheeva.git] / drivers / gpu / drm / radeon / rv770.c

diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index b13c2eedc3218ff558340da52f4bf2955cce1ada..9e4c0418f54d52e5cc5fad7b368248365a1fae67 100644 (file)
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -47,6 +47,7 @@ u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
 {
        struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
        u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
+       int i;
 
        /* Lock the graphics update lock */
        tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
@@ -66,7 +67,11 @@ u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
               (u32)crtc_base);
 
        /* Wait for update_pending to go high. */
-       while (!(RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING));
+       for (i = 0; i < rdev->usec_timeout; i++) {
+               if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
+                       break;
+               udelay(1);
+       }
        DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
 
        /* Unlock the lock, so double-buffering can take place inside vblank */
@@ -124,7 +129,7 @@ int rv770_pcie_gart_enable(struct radeon_device *rdev)
        u32 tmp;
        int r, i;
 
-       if (rdev->gart.table.vram.robj == NULL) {
+       if (rdev->gart.robj == NULL) {
                dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
                return -EINVAL;
        }
@@ -161,6 +166,9 @@ int rv770_pcie_gart_enable(struct radeon_device *rdev)
                WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 
        r600_pcie_gart_tlb_flush(rdev);
+       DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
+                (unsigned)(rdev->mc.gtt_size >> 20),
+                (unsigned long long)rdev->gart.table_addr);
        rdev->gart.ready = true;
        return 0;
 }
@@ -168,7 +176,7 @@ int rv770_pcie_gart_enable(struct radeon_device *rdev)
 void rv770_pcie_gart_disable(struct radeon_device *rdev)
 {
        u32 tmp;
-       int i, r;
+       int i;
 
        /* Disable all tables */
        for (i = 0; i < 7; i++)
@@ -188,14 +196,7 @@ void rv770_pcie_gart_disable(struct radeon_device *rdev)
        WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
        WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
        WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
-       if (rdev->gart.table.vram.robj) {
-               r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
-               if (likely(r == 0)) {
-                       radeon_bo_kunmap(rdev->gart.table.vram.robj);
-                       radeon_bo_unpin(rdev->gart.table.vram.robj);
-                       radeon_bo_unreserve(rdev->gart.table.vram.robj);
-               }
-       }
+       radeon_gart_table_vram_unpin(rdev);
 }
 
 void rv770_pcie_gart_fini(struct radeon_device *rdev)
@@ -279,7 +280,7 @@ static void rv770_mc_program(struct radeon_device *rdev)
                WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
                        rdev->mc.vram_end >> 12);
        }
-       WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
+       WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
        tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
        tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
        WREG32(MC_VM_FB_LOCATION, tmp);
@@ -356,7 +357,7 @@ static int rv770_cp_load_microcode(struct radeon_device *rdev)
 void r700_cp_fini(struct radeon_device *rdev)
 {
        r700_cp_stop(rdev);
-       radeon_ring_fini(rdev);
+       radeon_ring_fini(rdev, &rdev->cp[RADEON_RING_TYPE_GFX_INDEX]);
 }
 
 /*
@@ -956,54 +957,6 @@ static void rv770_gpu_init(struct radeon_device *rdev)
 
 }
 
-static int rv770_vram_scratch_init(struct radeon_device *rdev)
-{
-       int r;
-       u64 gpu_addr;
-
-       if (rdev->vram_scratch.robj == NULL) {
-               r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE,
-                                    PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
-                                    &rdev->vram_scratch.robj);
-               if (r) {
-                       return r;
-               }
-       }
-
-       r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
-       if (unlikely(r != 0))
-               return r;
-       r = radeon_bo_pin(rdev->vram_scratch.robj,
-                         RADEON_GEM_DOMAIN_VRAM, &gpu_addr);
-       if (r) {
-               radeon_bo_unreserve(rdev->vram_scratch.robj);
-               return r;
-       }
-       r = radeon_bo_kmap(rdev->vram_scratch.robj,
-                               (void **)&rdev->vram_scratch.ptr);
-       if (r)
-               radeon_bo_unpin(rdev->vram_scratch.robj);
-       radeon_bo_unreserve(rdev->vram_scratch.robj);
-
-       return r;
-}
-
-static void rv770_vram_scratch_fini(struct radeon_device *rdev)
-{
-       int r;
-
-       if (rdev->vram_scratch.robj == NULL) {
-               return;
-       }
-       r = radeon_bo_reserve(rdev->vram_scratch.robj, false);
-       if (likely(r == 0)) {
-               radeon_bo_kunmap(rdev->vram_scratch.robj);
-               radeon_bo_unpin(rdev->vram_scratch.robj);
-               radeon_bo_unreserve(rdev->vram_scratch.robj);
-       }
-       radeon_bo_unref(&rdev->vram_scratch.robj);
-}
-
 void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
 {
        u64 size_bf, size_af;
@@ -1090,6 +1043,7 @@ int rv770_mc_init(struct radeon_device *rdev)
 
 static int rv770_startup(struct radeon_device *rdev)
 {
+       struct radeon_cp *cp = &rdev->cp[RADEON_RING_TYPE_GFX_INDEX];
        int r;
 
        /* enable pcie gen2 link */
@@ -1103,6 +1057,10 @@ static int rv770_startup(struct radeon_device *rdev)
                }
        }
 
+       r = r600_vram_scratch_init(rdev);
+       if (r)
+               return r;
+
        rv770_mc_program(rdev);
        if (rdev->flags & RADEON_IS_AGP) {
                rv770_agp_enable(rdev);
@@ -1111,9 +1069,7 @@ static int rv770_startup(struct radeon_device *rdev)
                if (r)
                        return r;
        }
-       r = rv770_vram_scratch_init(rdev);
-       if (r)
-               return r;
+
        rv770_gpu_init(rdev);
        r = r600_blit_init(rdev);
        if (r) {
@@ -1136,7 +1092,8 @@ static int rv770_startup(struct radeon_device *rdev)
        }
        r600_irq_set(rdev);
 
-       r = radeon_ring_init(rdev, rdev->cp.ring_size);
+       r = radeon_ring_init(rdev, cp, cp->ring_size, RADEON_WB_CP_RPTR_OFFSET,
+                            R600_CP_RB_RPTR, R600_CP_RB_WPTR);
        if (r)
                return r;
        r = rv770_cp_load_microcode(rdev);
@@ -1166,7 +1123,7 @@ int rv770_resume(struct radeon_device *rdev)
                return r;
        }
 
-       r = r600_ib_test(rdev);
+       r = r600_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX);
        if (r) {
                DRM_ERROR("radeon: failed testing IB (%d).\n", r);
                return r;
@@ -1184,23 +1141,15 @@ int rv770_resume(struct radeon_device *rdev)
 
 int rv770_suspend(struct radeon_device *rdev)
 {
-       int r;
-
        r600_audio_fini(rdev);
        /* FIXME: we should wait for ring to be empty */
        r700_cp_stop(rdev);
-       rdev->cp.ready = false;
+       rdev->cp[RADEON_RING_TYPE_GFX_INDEX].ready = false;
        r600_irq_suspend(rdev);
        radeon_wb_disable(rdev);
        rv770_pcie_gart_disable(rdev);
-       /* unpin shaders bo */
-       if (rdev->r600_blit.shader_obj) {
-               r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
-               if (likely(r == 0)) {
-                       radeon_bo_unpin(rdev->r600_blit.shader_obj);
-                       radeon_bo_unreserve(rdev->r600_blit.shader_obj);
-               }
-       }
+       r600_blit_suspend(rdev);
+
        return 0;
 }
 
@@ -1247,7 +1196,7 @@ int rv770_init(struct radeon_device *rdev)
        /* Initialize clocks */
        radeon_get_clock_info(rdev->ddev);
        /* Fence driver */
-       r = radeon_fence_driver_init(rdev);
+       r = radeon_fence_driver_init(rdev, 1);
        if (r)
                return r;
        /* initialize AGP */
@@ -1268,8 +1217,8 @@ int rv770_init(struct radeon_device *rdev)
        if (r)
                return r;
 
-       rdev->cp.ring_obj = NULL;
-       r600_ring_init(rdev, 1024 * 1024);
+       rdev->cp[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
+       r600_ring_init(rdev, &rdev->cp[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
 
        rdev->ih.ring_obj = NULL;
        r600_ih_ring_init(rdev, 64 * 1024);
@@ -1295,7 +1244,7 @@ int rv770_init(struct radeon_device *rdev)
                        dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
                        rdev->accel_working = false;
                } else {
-                       r = r600_ib_test(rdev);
+                       r = r600_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX);
                        if (r) {
                                dev_err(rdev->dev, "IB test failed (%d).\n", r);
                                rdev->accel_working = false;
@@ -1321,8 +1270,9 @@ void rv770_fini(struct radeon_device *rdev)
        radeon_ib_pool_fini(rdev);
        radeon_irq_kms_fini(rdev);
        rv770_pcie_gart_fini(rdev);
-       rv770_vram_scratch_fini(rdev);
+       r600_vram_scratch_fini(rdev);
        radeon_gem_fini(rdev);
+       radeon_semaphore_driver_fini(rdev);
        radeon_fence_driver_fini(rdev);
        radeon_agp_fini(rdev);
        radeon_bo_fini(rdev);