* for doing DMA.
*
* Copyright (C) 1998-2003 Paul Mackerras & Ben. Herrenschmidt
- * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
+ * Copyright (C) 2007-2008 Bartlomiej Zolnierkiewicz
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
#include <asm/mediabay.h>
#endif
-#include "../ide-timing.h"
-
#undef IDE_PMAC_DEBUG
#define DMA_WAIT_TIMEOUT 50
pmac_ide_selectproc(drive);
}
-static void
-pmac_outbsync(ide_drive_t *drive, u8 value, unsigned long port)
+static void pmac_outbsync(ide_hwif_t *hwif, u8 value, unsigned long port)
{
u32 tmp;
writeb(value, (void __iomem *) port);
- tmp = readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
+ tmp = readl((void __iomem *)(hwif->io_ports.data_addr
+ + IDE_TIMING_CONFIG));
}
/*
static void
pmac_ide_set_pio_mode(ide_drive_t *drive, const u8 pio)
{
+ struct ide_timing *tim = ide_timing_find_mode(XFER_PIO_0 + pio);
u32 *timings, t;
unsigned accessTicks, recTicks;
unsigned accessTime, recTime;
}
case controller_kl_ata4:
/* 66Mhz cell */
- recTime = cycle_time - ide_pio_timings[pio].active_time
- - ide_pio_timings[pio].setup_time;
+ recTime = cycle_time - tim->active - tim->setup;
recTime = max(recTime, 150U);
- accessTime = ide_pio_timings[pio].active_time;
+ accessTime = tim->active;
accessTime = max(accessTime, 150U);
accessTicks = SYSCLK_TICKS_66(accessTime);
accessTicks = min(accessTicks, 0x1fU);
default: {
/* 33Mhz cell */
int ebit = 0;
- recTime = cycle_time - ide_pio_timings[pio].active_time
- - ide_pio_timings[pio].setup_time;
+ recTime = cycle_time - tim->active - tim->setup;
recTime = max(recTime, 150U);
- accessTime = ide_pio_timings[pio].active_time;
+ accessTime = tim->active;
accessTime = max(accessTime, 150U);
accessTicks = SYSCLK_TICKS(accessTime);
accessTicks = min(accessTicks, 0x1fU);