u32 R0 = 0;
R0 = (a % c) << 4; /* 32-28 == 4 shifts possible at max */
- Q1 = a / c; /* integer part, only the 4 least significant bits
- will be visible in the result */
+ Q1 = a / c; /*
+ * integer part, only the 4 least significant
+ * bits will be visible in the result
+ */
/* division using radix 16, 7 nibbles in the result */
for (i = 0; i < 7; i++) {
data = 0;
status = i2c_write(state, state->demod_address,
&data, 1);
- msleep(10);
+ usleep_range(10000, 11000);
retry_count++;
if (status < 0)
continue;
/* Init AGC and PGA parameters */
/* VSB IF */
- state->m_vsb_if_agc_cfg.ctrl_mode = (ul_vsb_if_agc_mode);
- state->m_vsb_if_agc_cfg.output_level = (ul_vsb_if_agc_output_level);
- state->m_vsb_if_agc_cfg.min_output_level = (ul_vsb_if_agc_min_level);
- state->m_vsb_if_agc_cfg.max_output_level = (ul_vsb_if_agc_max_level);
- state->m_vsb_if_agc_cfg.speed = (ul_vsb_if_agc_speed);
+ state->m_vsb_if_agc_cfg.ctrl_mode = ul_vsb_if_agc_mode;
+ state->m_vsb_if_agc_cfg.output_level = ul_vsb_if_agc_output_level;
+ state->m_vsb_if_agc_cfg.min_output_level = ul_vsb_if_agc_min_level;
+ state->m_vsb_if_agc_cfg.max_output_level = ul_vsb_if_agc_max_level;
+ state->m_vsb_if_agc_cfg.speed = ul_vsb_if_agc_speed;
state->m_vsb_pga_cfg = 140;
/* VSB RF */
- state->m_vsb_rf_agc_cfg.ctrl_mode = (ul_vsb_rf_agc_mode);
- state->m_vsb_rf_agc_cfg.output_level = (ul_vsb_rf_agc_output_level);
- state->m_vsb_rf_agc_cfg.min_output_level = (ul_vsb_rf_agc_min_level);
- state->m_vsb_rf_agc_cfg.max_output_level = (ul_vsb_rf_agc_max_level);
- state->m_vsb_rf_agc_cfg.speed = (ul_vsb_rf_agc_speed);
- state->m_vsb_rf_agc_cfg.top = (ul_vsb_rf_agc_top);
- state->m_vsb_rf_agc_cfg.cut_off_current = (ul_vsb_rf_agc_cut_off_current);
+ state->m_vsb_rf_agc_cfg.ctrl_mode = ul_vsb_rf_agc_mode;
+ state->m_vsb_rf_agc_cfg.output_level = ul_vsb_rf_agc_output_level;
+ state->m_vsb_rf_agc_cfg.min_output_level = ul_vsb_rf_agc_min_level;
+ state->m_vsb_rf_agc_cfg.max_output_level = ul_vsb_rf_agc_max_level;
+ state->m_vsb_rf_agc_cfg.speed = ul_vsb_rf_agc_speed;
+ state->m_vsb_rf_agc_cfg.top = ul_vsb_rf_agc_top;
+ state->m_vsb_rf_agc_cfg.cut_off_current = ul_vsb_rf_agc_cut_off_current;
state->m_vsb_pre_saw_cfg.reference = 0x07;
state->m_vsb_pre_saw_cfg.use_pre_saw = true;
}
/* ATV IF */
- state->m_atv_if_agc_cfg.ctrl_mode = (ul_atv_if_agc_mode);
- state->m_atv_if_agc_cfg.output_level = (ul_atv_if_agc_output_level);
- state->m_atv_if_agc_cfg.min_output_level = (ul_atv_if_agc_min_level);
- state->m_atv_if_agc_cfg.max_output_level = (ul_atv_if_agc_max_level);
- state->m_atv_if_agc_cfg.speed = (ul_atv_if_agc_speed);
+ state->m_atv_if_agc_cfg.ctrl_mode = ul_atv_if_agc_mode;
+ state->m_atv_if_agc_cfg.output_level = ul_atv_if_agc_output_level;
+ state->m_atv_if_agc_cfg.min_output_level = ul_atv_if_agc_min_level;
+ state->m_atv_if_agc_cfg.max_output_level = ul_atv_if_agc_max_level;
+ state->m_atv_if_agc_cfg.speed = ul_atv_if_agc_speed;
/* ATV RF */
- state->m_atv_rf_agc_cfg.ctrl_mode = (ul_atv_rf_agc_mode);
- state->m_atv_rf_agc_cfg.output_level = (ul_atv_rf_agc_output_level);
- state->m_atv_rf_agc_cfg.min_output_level = (ul_atv_rf_agc_min_level);
- state->m_atv_rf_agc_cfg.max_output_level = (ul_atv_rf_agc_max_level);
- state->m_atv_rf_agc_cfg.speed = (ul_atv_rf_agc_speed);
- state->m_atv_rf_agc_cfg.top = (ul_atv_rf_agc_top);
- state->m_atv_rf_agc_cfg.cut_off_current = (ul_atv_rf_agc_cut_off_current);
+ state->m_atv_rf_agc_cfg.ctrl_mode = ul_atv_rf_agc_mode;
+ state->m_atv_rf_agc_cfg.output_level = ul_atv_rf_agc_output_level;
+ state->m_atv_rf_agc_cfg.min_output_level = ul_atv_rf_agc_min_level;
+ state->m_atv_rf_agc_cfg.max_output_level = ul_atv_rf_agc_max_level;
+ state->m_atv_rf_agc_cfg.speed = ul_atv_rf_agc_speed;
+ state->m_atv_rf_agc_cfg.top = ul_atv_rf_agc_top;
+ state->m_atv_rf_agc_cfg.cut_off_current = ul_atv_rf_agc_cut_off_current;
state->m_atv_pre_saw_cfg.reference = 0x04;
state->m_atv_pre_saw_cfg.use_pre_saw = true;
state->m_sqi_speed = DRXK_DVBT_SQI_SPEED_MEDIUM;
state->m_agcfast_clip_ctrl_delay = 0;
- state->m_gpio_cfg = (ul_gpio_cfg);
+ state->m_gpio_cfg = ul_gpio_cfg;
state->m_b_power_down = false;
state->m_current_power_mode = DRX_POWER_DOWN;
dprintk(1, "\n");
/* stop lock indicator process */
- status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
+ status = write16(state, SCU_RAM_GPIO__A,
+ SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
if (status < 0)
goto error;
/* Check device id */
/* driver 0.9.0 */
/* stop lock indicator process */
- status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
+ status = write16(state, SCU_RAM_GPIO__A,
+ SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
if (status < 0)
goto error;
status = write16(state, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY);
if (status < 0)
goto error;
if (cmd == SIO_HI_RA_RAM_CMD_RESET)
- msleep(1);
+ usleep_range(1000, 2000);
powerdown_cmd =
(bool) ((cmd == SIO_HI_RA_RAM_CMD_CONFIG) &&
u16 wait_cmd;
do {
- msleep(1);
+ usleep_range(1000, 2000);
retry_count += 1;
status = read16(state, SIO_HI_RA_RAM_CMD__A,
&wait_cmd);
mutex_lock(&state->mutex);
- status = write16(state, SIO_HI_RA_RAM_PAR_6__A, state->m_hi_cfg_timeout);
+ status = write16(state, SIO_HI_RA_RAM_PAR_6__A,
+ state->m_hi_cfg_timeout);
if (status < 0)
goto error;
- status = write16(state, SIO_HI_RA_RAM_PAR_5__A, state->m_hi_cfg_ctrl);
+ status = write16(state, SIO_HI_RA_RAM_PAR_5__A,
+ state->m_hi_cfg_ctrl);
if (status < 0)
goto error;
- status = write16(state, SIO_HI_RA_RAM_PAR_4__A, state->m_hi_cfg_wake_up_key);
+ status = write16(state, SIO_HI_RA_RAM_PAR_4__A,
+ state->m_hi_cfg_wake_up_key);
if (status < 0)
goto error;
- status = write16(state, SIO_HI_RA_RAM_PAR_3__A, state->m_hi_cfg_bridge_delay);
+ status = write16(state, SIO_HI_RA_RAM_PAR_3__A,
+ state->m_hi_cfg_bridge_delay);
if (status < 0)
goto error;
- status = write16(state, SIO_HI_RA_RAM_PAR_2__A, state->m_hi_cfg_timing_div);
+ status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
+ state->m_hi_cfg_timing_div);
if (status < 0)
goto error;
- status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
+ status = write16(state, SIO_HI_RA_RAM_PAR_1__A,
+ SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
if (status < 0)
goto error;
status = hi_command(state, SIO_HI_RA_RAM_CMD_CONFIG, 0);
state->m_enable_parallel ? "parallel" : "serial");
/* stop lock indicator process */
- status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
+ status = write16(state, SCU_RAM_GPIO__A,
+ SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
if (status < 0)
goto error;
if (state->m_enable_parallel == true) {
/* paralel -> enable MD1 to MD7 */
- status = write16(state, SIO_PDR_MD1_CFG__A, sio_pdr_mdx_cfg);
+ status = write16(state, SIO_PDR_MD1_CFG__A,
+ sio_pdr_mdx_cfg);
if (status < 0)
goto error;
- status = write16(state, SIO_PDR_MD2_CFG__A, sio_pdr_mdx_cfg);
+ status = write16(state, SIO_PDR_MD2_CFG__A,
+ sio_pdr_mdx_cfg);
if (status < 0)
goto error;
- status = write16(state, SIO_PDR_MD3_CFG__A, sio_pdr_mdx_cfg);
+ status = write16(state, SIO_PDR_MD3_CFG__A,
+ sio_pdr_mdx_cfg);
if (status < 0)
goto error;
- status = write16(state, SIO_PDR_MD4_CFG__A, sio_pdr_mdx_cfg);
+ status = write16(state, SIO_PDR_MD4_CFG__A,
+ sio_pdr_mdx_cfg);
if (status < 0)
goto error;
- status = write16(state, SIO_PDR_MD5_CFG__A, sio_pdr_mdx_cfg);
+ status = write16(state, SIO_PDR_MD5_CFG__A,
+ sio_pdr_mdx_cfg);
if (status < 0)
goto error;
- status = write16(state, SIO_PDR_MD6_CFG__A, sio_pdr_mdx_cfg);
+ status = write16(state, SIO_PDR_MD6_CFG__A,
+ sio_pdr_mdx_cfg);
if (status < 0)
goto error;
- status = write16(state, SIO_PDR_MD7_CFG__A, sio_pdr_mdx_cfg);
+ status = write16(state, SIO_PDR_MD7_CFG__A,
+ sio_pdr_mdx_cfg);
if (status < 0)
goto error;
} else {
end = jiffies + msecs_to_jiffies(time_out);
do {
- msleep(1);
+ usleep_range(1000, 2000);
status = read16(state, SIO_BL_STATUS__A, &bl_status);
if (status < 0)
goto error;
end = jiffies + msecs_to_jiffies(DRXK_OFDM_TR_SHUTDOWN_TIMEOUT);
do {
status = read16(state, SIO_OFDM_SH_OFDM_RING_STATUS__A, &data);
- if ((status >= 0 && data == desired_status) || time_is_after_jiffies(end))
+ if ((status >= 0 && data == desired_status)
+ || time_is_after_jiffies(end))
break;
- msleep(1);
+ usleep_range(1000, 2000);
} while (1);
if (data != desired_status) {
pr_err("SIO not ready\n");
/* Wait until SCU has processed command */
end = jiffies + msecs_to_jiffies(DRXK_MAX_WAITTIME);
do {
- msleep(1);
+ usleep_range(1000, 2000);
status = read16(state, SCU_RAM_COMMAND__A, &cur_cmd);
if (status < 0)
goto error;
int ii;
for (ii = result_len - 1; ii >= 0; ii -= 1) {
- status = read16(state, SCU_RAM_PARAM_0__A - ii, &result[ii]);
+ status = read16(state, SCU_RAM_PARAM_0__A - ii,
+ &result[ii]);
if (status < 0)
goto error;
}
goto error;
if (data == SCU_COMM_EXEC_ACTIVE) {
/* Send OFDM stop command */
- status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmd_result);
+ status = scu_command(state,
+ SCU_RAM_COMMAND_STANDARD_OFDM
+ | SCU_RAM_COMMAND_CMD_DEMOD_STOP,
+ 0, NULL, 1, &cmd_result);
if (status < 0)
goto error;
/* Send OFDM reset command */
- status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmd_result);
+ status = scu_command(state,
+ SCU_RAM_COMMAND_STANDARD_OFDM
+ | SCU_RAM_COMMAND_CMD_DEMOD_RESET,
+ 0, NULL, 1, &cmd_result);
if (status < 0)
goto error;
}
*/
/* disable HW lock indicator */
- status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
+ status = write16(state, SCU_RAM_GPIO__A,
+ SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
if (status < 0)
goto error;
status = write32(state, FEC_OC_RCN_CTL_RATE_LO__A, fec_oc_rcn_ctl_rate);
if (status < 0)
goto error;
- status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A, fec_oc_tmd_int_upd_rate);
+ status = write16(state, FEC_OC_TMD_INT_UPD_RATE__A,
+ fec_oc_tmd_int_upd_rate);
if (status < 0)
goto error;
status = write16(state, FEC_OC_TMD_MODE__A, fec_oc_tmd_mode);
/* Set TOP, only if IF-AGC is in AUTO mode */
if (p_if_agc_settings->ctrl_mode == DRXK_AGC_CTRL_AUTO)
- status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, p_agc_cfg->top);
+ status = write16(state,
+ SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
+ p_agc_cfg->top);
if (status < 0)
goto error;
/* Cut-Off current */
- status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A, p_agc_cfg->cut_off_current);
+ status = write16(state, SCU_RAM_AGC_RF_IACCU_HI_CO__A,
+ p_agc_cfg->cut_off_current);
if (status < 0)
goto error;
/* Max. output level */
- status = write16(state, SCU_RAM_AGC_RF_MAX__A, p_agc_cfg->max_output_level);
+ status = write16(state, SCU_RAM_AGC_RF_MAX__A,
+ p_agc_cfg->max_output_level);
if (status < 0)
goto error;
goto error;
/* Write value to output pin */
- status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A, p_agc_cfg->output_level);
+ status = write16(state, SCU_RAM_AGC_RF_IACCU_HI__A,
+ p_agc_cfg->output_level);
if (status < 0)
goto error;
break;
if (p_rf_agc_settings == NULL)
return -1;
/* Restore TOP */
- status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, p_rf_agc_settings->top);
+ status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
+ p_rf_agc_settings->top);
if (status < 0)
goto error;
break;
goto error;
/* Write value to output pin */
- status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, p_agc_cfg->output_level);
+ status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
+ p_agc_cfg->output_level);
if (status < 0)
goto error;
break;
dprintk(1, "\n");
- status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A, &eq_reg_td_tps_pwr_ofs);
+ status = read16(state, OFDM_EQ_TOP_TD_TPS_PWR_OFS__A,
+ &eq_reg_td_tps_pwr_ofs);
if (status < 0)
goto error;
- status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A, &eq_reg_td_req_smb_cnt);
+ status = read16(state, OFDM_EQ_TOP_TD_REQ_SMB_CNT__A,
+ &eq_reg_td_req_smb_cnt);
if (status < 0)
goto error;
- status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A, &eq_reg_td_sqr_err_exp);
+ status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_EXP__A,
+ &eq_reg_td_sqr_err_exp);
if (status < 0)
goto error;
- status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A, ®_data);
+ status = read16(state, OFDM_EQ_TOP_TD_SQR_ERR_I__A,
+ ®_data);
if (status < 0)
goto error;
/* Extend SQR_ERR_I operational range */
(eq_reg_td_sqr_err_q < 0x00000FFFUL))
eq_reg_td_sqr_err_q += 0x00010000UL;
- status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A, &transmission_params);
+ status = read16(state, OFDM_SC_RA_RAM_OP_PARAM__A,
+ &transmission_params);
if (status < 0)
goto error;
status = get_dvbt_signal_to_noise(state, &signal_to_noise);
if (status < 0)
break;
- status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A, &constellation);
+ status = read16(state, OFDM_EQ_TOP_TD_TPS_CONST__A,
+ &constellation);
if (status < 0)
break;
constellation &= OFDM_EQ_TOP_TD_TPS_CONST__M;
- status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A, &code_rate);
+ status = read16(state, OFDM_EQ_TOP_TD_TPS_CODE_HP__A,
+ &code_rate);
if (status < 0)
break;
code_rate &= OFDM_EQ_TOP_TD_TPS_CODE_HP__M;
if (state->no_i2c_bridge)
return 0;
- status = write16(state, SIO_HI_RA_RAM_PAR_1__A, SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
+ status = write16(state, SIO_HI_RA_RAM_PAR_1__A,
+ SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY);
if (status < 0)
goto error;
if (b_enable_bridge) {
- status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED);
+ status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
+ SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED);
if (status < 0)
goto error;
} else {
- status = write16(state, SIO_HI_RA_RAM_PAR_2__A, SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN);
+ status = write16(state, SIO_HI_RA_RAM_PAR_2__A,
+ SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN);
if (status < 0)
goto error;
}
ingain_tgt_max = 5119;
fast_clp_ctrl_delay = state->m_qam_if_agc_cfg.fast_clip_ctrl_delay;
- status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, fast_clp_ctrl_delay);
+ status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,
+ fast_clp_ctrl_delay);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max);
if (status < 0)
goto error;
- status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, if_iaccu_hi_tgt_min);
+ status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A,
+ if_iaccu_hi_tgt_min);
if (status < 0)
goto error;
- status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, if_iaccu_hi_tgt_max);
+ status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A,
+ if_iaccu_hi_tgt_max);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_AGC_IF_IACCU_HI__A, 0);
if (status < 0)
goto error;
- status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, ki_innergain_min);
+ status = write16(state, SCU_RAM_AGC_KI_INNERGAIN_MIN__A,
+ ki_innergain_min);
if (status < 0)
goto error;
- status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, if_iaccu_hi_tgt);
+ status = write16(state, SCU_RAM_AGC_IF_IACCU_HI_TGT__A,
+ if_iaccu_hi_tgt);
if (status < 0)
goto error;
status = write16(state, SCU_RAM_AGC_CLP_CYCLEN__A, clp_cyclen);
if (packet_err == NULL)
status = write16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0);
else
- status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, packet_err);
+ status = read16(state, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A,
+ packet_err);
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
return status;
/* Wait until sc is ready to receive command */
retry_cnt = 0;
do {
- msleep(1);
+ usleep_range(1000, 2000);
status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd);
retry_cnt++;
} while ((cur_cmd != 0) && (retry_cnt < DRXK_MAX_RETRIES));
/* Wait until sc is ready processing command */
retry_cnt = 0;
do {
- msleep(1);
+ usleep_range(1000, 2000);
status = read16(state, OFDM_SC_RA_RAM_CMD__A, &cur_cmd);
retry_cnt++;
} while ((cur_cmd != 0) && (retry_cnt < DRXK_MAX_RETRIES));
}
static int dvbt_ctrl_set_echo_threshold(struct drxk_state *state,
- struct drxk_cfg_dvbt_echo_thres_t *echo_thres)
+ struct drxk_cfg_dvbt_echo_thres_t *echo_thres)
{
u16 data = 0;
int status;
status = dvbt_ctrl_set_echo_threshold(state, &echo_thres8k);
if (status < 0)
goto error;
- status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A, state->m_dvbt_if_agc_cfg.ingain_tgt_max);
+ status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MAX__A,
+ state->m_dvbt_if_agc_cfg.ingain_tgt_max);
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
/* added antenna switch */
switch_antenna_to_dvbt(state);
/* send OFDM reset command */
- status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmd_result);
+ status = scu_command(state,
+ SCU_RAM_COMMAND_STANDARD_OFDM
+ | SCU_RAM_COMMAND_CMD_DEMOD_RESET,
+ 0, NULL, 1, &cmd_result);
if (status < 0)
goto error;
/* send OFDM setenv command */
- status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV, 0, NULL, 1, &cmd_result);
+ status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
+ | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV,
+ 0, NULL, 1, &cmd_result);
if (status < 0)
goto error;
status = write16(state, IQM_RC_STRETCH__A, 16);
if (status < 0)
goto error;
- status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */
+ status = write16(state, IQM_CF_OUT_ENA__A, 0x4); /* enable output 2 */
if (status < 0)
goto error;
status = write16(state, IQM_CF_DS_ENA__A, 0x4); /* decimate output 2 */
if (status < 0)
goto error;
- status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
+ status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_DVBT,
+ DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
if (status < 0)
goto error;
if (!state->m_drxk_a3_rom_code) {
/* AGCInit() is not done for DVBT, so set agcfast_clip_ctrl_delay */
- status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay);
+ status = write16(state, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A,
+ state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay);
if (status < 0)
goto error;
}
/* start correct processes to get in lock */
/* DRXK: OFDM_SC_RA_RAM_PROC_LOCKTRACK is no longer in mapfile! */
param1 = OFDM_SC_RA_RAM_LOCKTRACK_MIN;
- status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0, OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M, param1, 0, 0, 0);
+ status = dvbt_sc_command(state, OFDM_SC_RA_RAM_CMD_PROC_START, 0,
+ OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M, param1,
+ 0, 0, 0);
if (status < 0)
goto error;
/* start FEC OC */
u16 param1;
int status;
- dprintk(1, "IF =%d, TFO = %d\n", intermediate_freqk_hz, tuner_freq_offset);
+ dprintk(1, "IF =%d, TFO = %d\n",
+ intermediate_freqk_hz, tuner_freq_offset);
- status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmd_result);
+ status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
+ | SCU_RAM_COMMAND_CMD_DEMOD_STOP,
+ 0, NULL, 1, &cmd_result);
if (status < 0)
goto error;
if (status < 0)
goto error;
- /*== Write channel settings to device =====================================*/
+ /*== Write channel settings to device ================================*/
/* mode */
switch (state->props.transmission_mode) {
break;
}
- /* SAW filter selection: normaly not necesarry, but if wanted
- the application can select a SAW filter via the driver by using UIOs */
+ /*
+ * SAW filter selection: normaly not necesarry, but if wanted
+ * the application can select a SAW filter via the driver by
+ * using UIOs
+ */
+
/* First determine real bandwidth (Hz) */
/* Also set delay for impulse noise cruncher */
- /* Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is changed
- by SC for fix for some 8K,1/8 guard but is restored by InitEC and ResetEC
- functions */
+ /*
+ * Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is
+ * changed by SC for fix for some 8K,1/8 guard but is restored by
+ * InitEC and ResetEC functions
+ */
switch (state->props.bandwidth_hz) {
case 0:
state->props.bandwidth_hz = 8000000;
/* fall though */
case 8000000:
bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ;
- status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3052);
+ status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
+ 3052);
if (status < 0)
goto error;
/* cochannel protection for PAL 8 MHz */
- status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 7);
+ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
+ 7);
if (status < 0)
goto error;
- status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 7);
+ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
+ 7);
if (status < 0)
goto error;
- status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 7);
+ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
+ 7);
if (status < 0)
goto error;
- status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
+ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
+ 1);
if (status < 0)
goto error;
break;
case 7000000:
bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ;
- status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3491);
+ status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
+ 3491);
if (status < 0)
goto error;
/* cochannel protection for PAL 7 MHz */
- status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 8);
+ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
+ 8);
if (status < 0)
goto error;
- status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 8);
+ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
+ 8);
if (status < 0)
goto error;
- status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 4);
+ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
+ 4);
if (status < 0)
goto error;
- status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
+ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
+ 1);
if (status < 0)
goto error;
break;
case 6000000:
bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ;
- status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 4073);
+ status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A,
+ 4073);
if (status < 0)
goto error;
/* cochannel protection for NTSC 6 MHz */
- status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A, 19);
+ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A,
+ 19);
if (status < 0)
goto error;
- status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A, 19);
+ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A,
+ 19);
if (status < 0)
goto error;
- status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A, 14);
+ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A,
+ 14);
if (status < 0)
goto error;
- status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A, 1);
+ status = write16(state, OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A,
+ 1);
if (status < 0)
goto error;
break;
((SysFreq / BandWidth) * (2^21)) - (2^23)
*/
/* (SysFreq / BandWidth) * (2^28) */
- /* assert (MAX(sysClk)/MIN(bandwidth) < 16)
- => assert(MAX(sysClk) < 16*MIN(bandwidth))
- => assert(109714272 > 48000000) = true so Frac 28 can be used */
+ /*
+ * assert (MAX(sysClk)/MIN(bandwidth) < 16)
+ * => assert(MAX(sysClk) < 16*MIN(bandwidth))
+ * => assert(109714272 > 48000000) = true
+ * so Frac 28 can be used
+ */
iqm_rc_rate_ofs = Frac28a((u32)
((state->m_sys_clock_freq *
1000) / 3), bandwidth);
- /* (SysFreq / BandWidth) * (2^21), rounding before truncating */
+ /* (SysFreq / BandWidth) * (2^21), rounding before truncating */
if ((iqm_rc_rate_ofs & 0x7fL) >= 0x40)
iqm_rc_rate_ofs += 0x80L;
iqm_rc_rate_ofs = iqm_rc_rate_ofs >> 7;
if (status < 0)
goto error;
#endif
- status = set_frequency_shifter(state, intermediate_freqk_hz, tuner_freq_offset, true);
+ status = set_frequency_shifter(state, intermediate_freqk_hz,
+ tuner_freq_offset, true);
if (status < 0)
goto error;
- /*== start SC, write channel settings to SC ===============================*/
+ /*== start SC, write channel settings to SC ==========================*/
/* Activate SCU to enable SCU commands */
status = write16(state, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE);
goto error;
- status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmd_result);
+ status = scu_command(state, SCU_RAM_COMMAND_STANDARD_OFDM
+ | SCU_RAM_COMMAND_CMD_DEMOD_START,
+ 0, NULL, 1, &cmd_result);
if (status < 0)
goto error;
status = write16(state, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP);
if (status < 0)
goto error;
- status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_STOP, 0, NULL, 1, &cmd_result);
+ status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
+ | SCU_RAM_COMMAND_CMD_DEMOD_STOP,
+ 0, NULL, 1, &cmd_result);
if (status < 0)
goto error;
}
if (status < 0)
goto error;
- fec_bits_desired /= 1000; /* symbol_rate [Hz] -> symbol_rate [kHz] */
+ fec_bits_desired /= 1000; /* symbol_rate [Hz] -> symbol_rate [kHz] */
fec_bits_desired *= 500; /* meas. period [ms] */
/* Annex A/C: bits/RsPeriod = 204 * 8 = 1632 */
status = write16(state, FEC_RS_MEASUREMENT_PERIOD__A, fec_rs_period);
if (status < 0)
goto error;
- status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A, fec_rs_prescale);
+ status = write16(state, FEC_RS_MEASUREMENT_PRESCALE__A,
+ fec_rs_prescale);
if (status < 0)
goto error;
status = write16(state, FEC_OC_SNC_FAIL_PERIOD__A, fec_rs_period);
goto error;
/* QAM Slicer Settings */
- status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM16);
+ status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
+ DRXK_QAM_SL_SIG_POWER_QAM16);
if (status < 0)
goto error;
/* QAM Slicer Settings */
- status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM32);
+ status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
+ DRXK_QAM_SL_SIG_POWER_QAM32);
if (status < 0)
goto error;
goto error;
/* QAM Slicer Settings */
- status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM64);
+ status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
+ DRXK_QAM_SL_SIG_POWER_QAM64);
if (status < 0)
goto error;
/* QAM Slicer Settings */
- status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM128);
+ status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
+ DRXK_QAM_SL_SIG_POWER_QAM128);
if (status < 0)
goto error;
/* QAM Slicer Settings */
- status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A, DRXK_QAM_SL_SIG_POWER_QAM256);
+ status = write16(state, SCU_RAM_QAM_SL_SIG_POWER__A,
+ DRXK_QAM_SL_SIG_POWER_QAM256);
if (status < 0)
goto error;
if (status < 0)
goto error;
- status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_RESET, 0, NULL, 1, &cmd_result);
+ status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
+ | SCU_RAM_COMMAND_CMD_DEMOD_RESET,
+ 0, NULL, 1, &cmd_result);
error:
if (status < 0)
pr_err("Error %d on %s\n", status, __func__);
} else {
/* 0xC000 NEVER LOCKED */
/* (system will never be able to lock to the signal) */
- /* TODO: check this, intermediate & standard specific lock states are not
- taken into account here */
+ /*
+ * TODO: check this, intermediate & standard specific lock
+ * states are not taken into account here
+ */
*p_lock_status = NEVER_LOCK;
}
return status;
set_env_parameters[0] = QAM_TOP_ANNEX_A;
status = scu_command(state,
- SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV,
+ SCU_RAM_COMMAND_STANDARD_QAM
+ | SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV,
1, set_env_parameters, 1, &cmd_result);
if (status < 0)
goto error;
status = scu_command(state,
- SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,
+ SCU_RAM_COMMAND_STANDARD_QAM
+ | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,
number_of_parameters, set_param_parameters,
1, &cmd_result);
} else if (number_of_parameters == 4) {
/* set_param_parameters[3] |= QAM_LOCKRANGE_NORMAL; */
status = scu_command(state,
- SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,
+ SCU_RAM_COMMAND_STANDARD_QAM
+ | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM,
number_of_parameters, set_param_parameters,
1, &cmd_result);
} else {
if (status < 0)
goto error;
#endif
- status = set_frequency_shifter(state, intermediate_freqk_hz, tuner_freq_offset, true);
+ status = set_frequency_shifter(state, intermediate_freqk_hz,
+ tuner_freq_offset, true);
if (status < 0)
goto error;
/* Setup BER measurement */
- status = set_qam_measurement(state, state->m_constellation, state->props.symbol_rate);
+ status = set_qam_measurement(state, state->m_constellation,
+ state->props.symbol_rate);
if (status < 0)
goto error;
goto error;
/* Mirroring, QAM-block starting point not inverted */
- status = write16(state, QAM_SY_SP_INV__A, QAM_SY_SP_INV_SPECTRUM_INV_DIS);
+ status = write16(state, QAM_SY_SP_INV__A,
+ QAM_SY_SP_INV_SPECTRUM_INV_DIS);
if (status < 0)
goto error;
goto error;
/* STEP 5: start QAM demodulator (starts FEC, QAM and IQM HW) */
- status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_START, 0, NULL, 1, &cmd_result);
+ status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM
+ | SCU_RAM_COMMAND_CMD_DEMOD_START,
+ 0, NULL, 1, &cmd_result);
if (status < 0)
goto error;
boot loader from ROM table */
switch (o_mode) {
case OM_QAM_ITU_A:
- status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A, DRXK_BLCC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
+ status = bl_chain_cmd(state, DRXK_BL_ROM_OFFSET_TAPS_ITU_A,
+ DRXK_BLCC_NR_ELEMENTS_TAPS,
+ DRXK_BLC_TIMEOUT);
break;
case OM_QAM_ITU_C:
- status = bl_direct_cmd(state, IQM_CF_TAP_RE0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
+ status = bl_direct_cmd(state, IQM_CF_TAP_RE0__A,
+ DRXK_BL_ROM_OFFSET_TAPS_ITU_C,
+ DRXK_BLDC_NR_ELEMENTS_TAPS,
+ DRXK_BLC_TIMEOUT);
if (status < 0)
goto error;
- status = bl_direct_cmd(state, IQM_CF_TAP_IM0__A, DRXK_BL_ROM_OFFSET_TAPS_ITU_C, DRXK_BLDC_NR_ELEMENTS_TAPS, DRXK_BLC_TIMEOUT);
+ status = bl_direct_cmd(state,
+ IQM_CF_TAP_IM0__A,
+ DRXK_BL_ROM_OFFSET_TAPS_ITU_C,
+ DRXK_BLDC_NR_ELEMENTS_TAPS,
+ DRXK_BLC_TIMEOUT);
break;
default:
status = -EINVAL;
if (status < 0)
goto error;
- status = write16(state, IQM_CF_OUT_ENA__A, (1 << IQM_CF_OUT_ENA_QAM__B));
+ status = write16(state, IQM_CF_OUT_ENA__A, 1 << IQM_CF_OUT_ENA_QAM__B);
if (status < 0)
goto error;
status = write16(state, IQM_CF_SYMMETRIC__A, 0);
if (status < 0)
goto error;
- status = write16(state, IQM_CF_MIDTAP__A, ((1 << IQM_CF_MIDTAP_RE__B) | (1 << IQM_CF_MIDTAP_IM__B)));
+ status = write16(state, IQM_CF_MIDTAP__A,
+ ((1 << IQM_CF_MIDTAP_RE__B) | (1 << IQM_CF_MIDTAP_IM__B)));
if (status < 0)
goto error;
dprintk(1, "\n");
/* stop lock indicator process */
- status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
+ status = write16(state, SCU_RAM_GPIO__A,
+ SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
if (status < 0)
goto error;
if (state->m_has_sawsw) {
if (state->uio_mask & 0x0001) { /* UIO-1 */
/* write to io pad configuration register - output mode */
- status = write16(state, SIO_PDR_SMA_TX_CFG__A, state->m_gpio_cfg);
+ status = write16(state, SIO_PDR_SMA_TX_CFG__A,
+ state->m_gpio_cfg);
if (status < 0)
goto error;
}
if (state->uio_mask & 0x0002) { /* UIO-2 */
/* write to io pad configuration register - output mode */
- status = write16(state, SIO_PDR_SMA_RX_CFG__A, state->m_gpio_cfg);
+ status = write16(state, SIO_PDR_SMA_RX_CFG__A,
+ state->m_gpio_cfg);
if (status < 0)
goto error;
}
if (state->uio_mask & 0x0004) { /* UIO-3 */
/* write to io pad configuration register - output mode */
- status = write16(state, SIO_PDR_GPIO_CFG__A, state->m_gpio_cfg);
+ status = write16(state, SIO_PDR_GPIO_CFG__A,
+ state->m_gpio_cfg);
if (status < 0)
goto error;
if (status < 0)
goto error;
- status = write16(state, SIO_CC_PWD_MODE__A, SIO_CC_PWD_MODE_LEVEL_CLOCK);
+ status = write16(state, SIO_CC_PWD_MODE__A,
+ SIO_CC_PWD_MODE_LEVEL_CLOCK);
if (status < 0)
goto error;
status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
if (status < 0)
goto error;
/* Soft reset of OFDM-, sys- and osc-clockdomain */
- status = write16(state, SIO_CC_SOFT_RST__A, SIO_CC_SOFT_RST_OFDM__M | SIO_CC_SOFT_RST_SYS__M | SIO_CC_SOFT_RST_OSC__M);
+ status = write16(state, SIO_CC_SOFT_RST__A,
+ SIO_CC_SOFT_RST_OFDM__M
+ | SIO_CC_SOFT_RST_SYS__M
+ | SIO_CC_SOFT_RST_OSC__M);
if (status < 0)
goto error;
status = write16(state, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY);
if (status < 0)
goto error;
- /* TODO is this needed, if yes how much delay in worst case scenario */
- msleep(1);
+ /*
+ * TODO is this needed? If yes, how much delay in
+ * worst case scenario
+ */
+ usleep_range(1000, 2000);
state->m_drxk_a3_patch_code = true;
status = get_device_capabilities(state);
if (status < 0)
&& !(state->m_DRXK_A2_ROM_CODE))
#endif
{
- status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
+ status = write16(state, SCU_RAM_GPIO__A,
+ SCU_RAM_GPIO_HW_LOCK_IND_DISABLE);
if (status < 0)
goto error;
}
goto error;
/* enable token-ring bus through OFDM block for possible ucode upload */
- status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_ON);
+ status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,
+ SIO_OFDM_SH_OFDM_RING_ENABLE_ON);
if (status < 0)
goto error;
/* include boot loader section */
- status = write16(state, SIO_BL_COMM_EXEC__A, SIO_BL_COMM_EXEC_ACTIVE);
+ status = write16(state, SIO_BL_COMM_EXEC__A,
+ SIO_BL_COMM_EXEC_ACTIVE);
if (status < 0)
goto error;
status = bl_chain_cmd(state, 0, 6, 100);
}
/* disable token-ring bus through OFDM block for possible ucode upload */
- status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A, SIO_OFDM_SH_OFDM_RING_ENABLE_OFF);
+ status = write16(state, SIO_OFDM_SH_OFDM_RING_ENABLE__A,
+ SIO_OFDM_SH_OFDM_RING_ENABLE_OFF);
if (status < 0)
goto error;
(((DRXK_VERSION_MAJOR / 10) % 10) << 8) +
((DRXK_VERSION_MAJOR % 10) << 4) +
(DRXK_VERSION_MINOR % 10);
- status = write16(state, SCU_RAM_DRIVER_VER_HI__A, driver_version);
+ status = write16(state, SCU_RAM_DRIVER_VER_HI__A,
+ driver_version);
if (status < 0)
goto error;
driver_version =
(((DRXK_VERSION_PATCH / 100) % 10) << 8) +
(((DRXK_VERSION_PATCH / 10) % 10) << 4) +
(DRXK_VERSION_PATCH % 10);
- status = write16(state, SCU_RAM_DRIVER_VER_LO__A, driver_version);
+ status = write16(state, SCU_RAM_DRIVER_VER_LO__A,
+ driver_version);
if (status < 0)
goto error;
DRXK_VERSION_MAJOR, DRXK_VERSION_MINOR,
DRXK_VERSION_PATCH);
- /* Dirty fix of default values for ROM/PATCH microcode
- Dirty because this fix makes it impossible to setup suitable values
- before calling DRX_Open. This solution requires changes to RF AGC speed
- to be done via the CTRL function after calling DRX_Open */
+ /*
+ * Dirty fix of default values for ROM/PATCH microcode
+ * Dirty because this fix makes it impossible to setup
+ * suitable values before calling DRX_Open. This solution
+ * requires changes to RF AGC speed to be done via the CTRL
+ * function after calling DRX_Open
+ */
/* m_dvbt_rf_agc_cfg.speed = 3; */
case SYS_DVBC_ANNEX_C:
if (!state->m_has_dvbc)
return -EINVAL;
- state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ? true : false;
+ state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ?
+ true : false;
if (state->m_itut_annex_c)
setoperation_mode(state, OM_QAM_ITU_C);
else
if (if_agc.output_level > if_agc.max_output_level)
if_agc.output_level = if_agc.max_output_level;
- agc_range = (u32) (if_agc.max_output_level - if_agc.min_output_level);
+ agc_range = (u32)(if_agc.max_output_level - if_agc.min_output_level);
if (agc_range > 0) {
atten += 100UL *
((u32)(tuner_if_gain)) *
/* BER measurement is valid if at least FEC lock is achieved */
- /* OFDM_EC_VD_REQ_SMB_CNT__A and/or OFDM_EC_VD_REQ_BIT_CNT can be written
- to set nr of symbols or bits over which
- to measure EC_VD_REG_ERR_BIT_CNT__A . See CtrlSetCfg(). */
+ /*
+ * OFDM_EC_VD_REQ_SMB_CNT__A and/or OFDM_EC_VD_REQ_BIT_CNT can be
+ * written to set nr of symbols or bits over which to measure
+ * EC_VD_REG_ERR_BIT_CNT__A . See CtrlSetCfg().
+ */
/* Read registers for post/preViterbi BER calculation */
status = read16(state, OFDM_EC_VD_ERR_BIT_CNT__A, ®16);
return 0;
}
-static int drxk_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings
- *sets)
+static int drxk_get_tune_settings(struct dvb_frontend *fe,
+ struct dvb_frontend_tune_settings *sets)
{
struct drxk_state *state = fe->demodulator_priv;
struct dtv_frontend_properties *p = &fe->dtv_property_cache;
projects / karo-tx-linux.git / blobdiff