/*
- * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2004-2014 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
#include "ipu_prp_sw.h"
#define init_MUTEX(sem) sema_init(sem, 1)
-#define MXC_SENSOR_NUM 2
static struct platform_device_id imx_v4l2_devtype[] = {
{
csi_param.csi = cam->csi;
csi_param.mclk = 0;
- /*This may not work on other platforms. Check when adding a new one.*/
- /*The mclk clock was never set correclty in the ipu register*/
- /*for now we are going to use this mclk as pixel clock*/
- /*to set csi0_data_dest register.*/
- /*This is a workaround which should be fixed*/
pr_debug(" clock_curr=mclk=%d\n", ifparm.u.bt656.clock_curr);
- if (ifparm.u.bt656.clock_curr == 0) {
+ if (ifparm.u.bt656.clock_curr == 0)
csi_param.clk_mode = IPU_CSI_CLK_MODE_CCIR656_INTERLACED;
- /*protocol bt656 use 27Mhz pixel clock */
- csi_param.mclk = 27000000;
- } else {
+ else
csi_param.clk_mode = IPU_CSI_CLK_MODE_GATED_CLK;
- }
csi_param.pixclk_pol = ifparm.u.bt656.latch_clk_inv;
*/
static int mxc_v4l2_s_std(cam_data *cam, v4l2_std_id e)
{
- printk(KERN_ERR "In mxc_v4l2_s_std %Lx\n", e);
+ pr_debug("In mxc_v4l2_s_std %Lx\n", e);
+
if (e == V4L2_STD_PAL) {
pr_debug(" Setting standard to PAL %Lx\n", V4L2_STD_PAL);
cam->standard.id = V4L2_STD_PAL;
/* Move all the sensors behind this
* sensor one step forward
*/
- for (; i < cam->sensor_index - 1; i++)
+ for (; i <= MXC_SENSOR_NUM - 2; i++)
cam->all_sensors[i] = cam->all_sensors[i+1];
break;
}