fsl_esdhc: Use mmc_set_clock to set initial speed

[karo-tx-uboot.git] / drivers / mmc / fsl_esdhc.c

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 0f6f8b161c91a645746756cb50989e11aeea7561..73d5cd3826afb5efe5434e8c498f475f76f8b338 100644 (file)
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -72,8 +72,10 @@ uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
        uint xfertyp = 0;
 
        if (data) {
-               xfertyp |= XFERTYP_DPSEL | XFERTYP_DMAEN;
-
+               xfertyp |= XFERTYP_DPSEL;
+#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
+               xfertyp |= XFERTYP_DMAEN;
+#endif
                if (data->blocks > 1) {
                        xfertyp |= XFERTYP_MSBSEL;
                        xfertyp |= XFERTYP_BCEN;
@@ -97,12 +99,78 @@ uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
        return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
 }
 
+#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
+/*
+ * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
+ */
+static void
+esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
+{
+       struct fsl_esdhc *regs = mmc->priv;
+       uint blocks;
+       char *buffer;
+       uint databuf;
+       uint size;
+       uint irqstat;
+       uint timeout;
+
+       if (data->flags & MMC_DATA_READ) {
+               blocks = data->blocks;
+               buffer = data->dest;
+               while (blocks) {
+                       timeout = PIO_TIMEOUT;
+                       size = data->blocksize;
+                       irqstat = esdhc_read32(&regs->irqstat);
+                       while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)
+                               && --timeout);
+                       if (timeout <= 0) {
+                               printf("\nData Read Failed in PIO Mode.");
+                               return;
+                       }
+                       while (size && (!(irqstat & IRQSTAT_TC))) {
+                               udelay(100); /* Wait before last byte transfer complete */
+                               irqstat = esdhc_read32(&regs->irqstat);
+                               databuf = in_le32(&regs->datport);
+                               *((uint *)buffer) = databuf;
+                               buffer += 4;
+                               size -= 4;
+                       }
+                       blocks--;
+               }
+       } else {
+               blocks = data->blocks;
+               buffer = (char *)data->src;
+               while (blocks) {
+                       timeout = PIO_TIMEOUT;
+                       size = data->blocksize;
+                       irqstat = esdhc_read32(&regs->irqstat);
+                       while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)
+                               && --timeout);
+                       if (timeout <= 0) {
+                               printf("\nData Write Failed in PIO Mode.");
+                               return;
+                       }
+                       while (size && (!(irqstat & IRQSTAT_TC))) {
+                               udelay(100); /* Wait before last byte transfer complete */
+                               databuf = *((uint *)buffer);
+                               buffer += 4;
+                               size -= 4;
+                               irqstat = esdhc_read32(&regs->irqstat);
+                               out_le32(&regs->datport, databuf);
+                       }
+                       blocks--;
+               }
+       }
+}
+#endif
+
 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
 {
-       uint wml_value;
        int timeout;
        struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
        struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base;
+#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
+       uint wml_value;
 
        wml_value = data->blocksize/4;
 
@@ -124,6 +192,17 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
                                        wml_value << 16);
                esdhc_write32(&regs->dsaddr, (u32)data->src);
        }
+#else  /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
+       if (!(data->flags & MMC_DATA_READ)) {
+               if ((esdhc_read32(&regs->prsstat) & PRSSTAT_WPSPL) == 0) {
+                       printf("\nThe SD card is locked. "
+                               "Can not write to a locked card.\n\n");
+                       return TIMEOUT;
+               }
+               esdhc_write32(&regs->dsaddr, (u32)data->src);
+       } else
+               esdhc_write32(&regs->dsaddr, (u32)data->dest);
+#endif /* CONFIG_SYS_FSL_ESDHC_USE_PIO */
 
        esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);
 
@@ -220,6 +299,9 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
 
        /* Wait until all of the blocks are transferred */
        if (data) {
+#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
+               esdhc_pio_read_write(mmc, data);
+#else
                do {
                        irqstat = esdhc_read32(&regs->irqstat);
 
@@ -230,6 +312,7 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
                                return TIMEOUT;
                } while (!(irqstat & IRQSTAT_TC) &&
                                (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA));
+#endif
        }
 
        esdhc_write32(&regs->irqstat, -1);
@@ -301,10 +384,6 @@ static int esdhc_init(struct mmc *mmc)
        int ret = 0;
        u8 card_absent;
 
-       /* Enable cache snooping */
-       if (cfg && !cfg->no_snoop)
-               esdhc_write32(&regs->scr, 0x00000040);
-
        /* Reset the entire host controller */
        esdhc_write32(&regs->sysctl, SYSCTL_RSTA);
 
@@ -312,10 +391,14 @@ static int esdhc_init(struct mmc *mmc)
        while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
                udelay(1000);
 
+       /* Enable cache snooping */
+       if (cfg && !cfg->no_snoop)
+               esdhc_write32(&regs->scr, 0x00000040);
+
        esdhc_write32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
 
        /* Set the initial clock speed */
-       set_sysctl(mmc, 400000);
+       mmc_set_clock(mmc, 400000);
 
        /* Disable the BRR and BWR bits in IRQSTAT */
        esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);