Add GPL-2.0+ SPDX-License-Identifier to source files

[karo-tx-uboot.git] / drivers / mmc / fsl_esdhc.c

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 4e43e3eec94599da9b75527a2d99118bc188c41c..f87e647881cce82f2eac37a4fc5a4863072b82e2 100644 (file)
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -6,23 +6,7 @@
  * (C) Copyright 2003
  * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <config.h>
@@ -470,7 +454,7 @@ static int esdhc_init(struct mmc *mmc)
        int timeout = 1000;
 
        /* Reset the entire host controller */
-       esdhc_write32(&regs->sysctl, SYSCTL_RSTA);
+       esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
 
        /* Wait until the controller is available */
        while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)
@@ -481,7 +465,7 @@ static int esdhc_init(struct mmc *mmc)
        esdhc_write32(&regs->scr, 0x00000040);
 #endif
 
-       esdhc_write32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
+       esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
 
        /* Set the initial clock speed */
        mmc_set_clock(mmc, 400000);
@@ -515,7 +499,7 @@ static void esdhc_reset(struct fsl_esdhc *regs)
        unsigned long timeout = 100; /* wait max 100 ms */
 
        /* reset the controller */
-       esdhc_write32(&regs->sysctl, SYSCTL_RSTA);
+       esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
 
        /* hardware clears the bit when it is done */
        while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA) && --timeout)