#include <part.h>
#include <i2c.h>
#include <twl4030.h>
+#include <twl6030.h>
+#include <twl6035.h>
#include <asm/io.h>
#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+
+/* common definitions for all OMAPs */
+#define SYSCTL_SRC (1 << 25)
+#define SYSCTL_SRD (1 << 26)
/* If we fail after 1 second wait, something is really bad */
#define MAX_RETRY_MS 1000
-static int mmc_read_data(hsmmc_t *mmc_base, char *buf, unsigned int size);
-static int mmc_write_data(hsmmc_t *mmc_base, const char *buf, unsigned int siz);
+static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size);
+static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
+ unsigned int siz);
static struct mmc hsmmc_dev[2];
-unsigned char mmc_board_init(hsmmc_t *mmc_base)
+
+#if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
+static void omap4_vmmc_pbias_config(struct mmc *mmc)
{
-#if defined(CONFIG_TWL4030_POWER)
- twl4030_power_mmc_init();
+ u32 value = 0;
+ struct omap_sys_ctrl_regs *const ctrl =
+ (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
+
+
+ value = readl(&ctrl->control_pbiaslite);
+ value &= ~(MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ);
+ writel(value, &ctrl->control_pbiaslite);
+ /* set VMMC to 3V */
+ twl6030_power_mmc_init();
+ value = readl(&ctrl->control_pbiaslite);
+ value |= MMC1_PBIASLITE_VMODE | MMC1_PBIASLITE_PWRDNZ | MMC1_PWRDNZ;
+ writel(value, &ctrl->control_pbiaslite);
+}
+#endif
+
+#if defined(CONFIG_OMAP54XX) && defined(CONFIG_TWL6035_POWER)
+static void omap5_pbias_config(struct mmc *mmc)
+{
+ u32 value = 0;
+ struct omap_sys_ctrl_regs *const ctrl =
+ (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE;
+
+ value = readl(&ctrl->control_pbias);
+ value &= ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ);
+ value |= SDCARD_BIAS_HIZ_MODE;
+ writel(value, &ctrl->control_pbias);
+
+ twl6035_mmc1_poweron_ldo();
+
+ value = readl(&ctrl->control_pbias);
+ value &= ~SDCARD_BIAS_HIZ_MODE;
+ value |= SDCARD_PBIASLITE_VMODE | SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ;
+ writel(value, &ctrl->control_pbias);
+
+ value = readl(&ctrl->control_pbias);
+ if (value & (1 << 23)) {
+ value &= ~(SDCARD_PWRDNZ | SDCARD_BIAS_PWRDNZ);
+ value |= SDCARD_BIAS_HIZ_MODE;
+ writel(value, &ctrl->control_pbias);
+ }
+}
#endif
+unsigned char mmc_board_init(struct mmc *mmc)
+{
#if defined(CONFIG_OMAP34XX)
t2_t *t2_base = (t2_t *)T2_BASE;
struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
+ u32 pbias_lite;
- writel(readl(&t2_base->pbias_lite) | PBIASLITEPWRDNZ1 |
+ pbias_lite = readl(&t2_base->pbias_lite);
+ pbias_lite &= ~(PBIASLITEPWRDNZ1 | PBIASLITEPWRDNZ0);
+ writel(pbias_lite, &t2_base->pbias_lite);
+#endif
+#if defined(CONFIG_TWL4030_POWER)
+ twl4030_power_mmc_init();
+ mdelay(100); /* ramp-up delay from Linux code */
+#endif
+#if defined(CONFIG_OMAP34XX)
+ writel(pbias_lite | PBIASLITEPWRDNZ1 |
PBIASSPEEDCTRL0 | PBIASLITEPWRDNZ0,
&t2_base->pbias_lite);
writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
&t2_base->devconf1);
+ /* Change from default of 52MHz to 26MHz if necessary */
+ if (!(mmc->host_caps & MMC_MODE_HS_52MHz))
+ writel(readl(&t2_base->ctl_prog_io1) & ~CTLPROGIO1SPEEDCTRL,
+ &t2_base->ctl_prog_io1);
+
writel(readl(&prcm_base->fclken1_core) |
EN_MMC1 | EN_MMC2 | EN_MMC3,
&prcm_base->fclken1_core);
&prcm_base->iclken1_core);
#endif
-/* TODO add appropriate OMAP4 init - none currently necessary */
+#if defined(CONFIG_OMAP44XX) && defined(CONFIG_TWL6030_POWER)
+ /* PBIAS config needed for MMC1 only */
+ if (mmc->block_dev.dev == 0)
+ omap4_vmmc_pbias_config(mmc);
+#endif
+#if defined(CONFIG_OMAP54XX) && defined(CONFIG_TWL6035_POWER)
+ if (mmc->block_dev.dev == 0)
+ omap5_pbias_config(mmc);
+#endif
return 0;
}
-void mmc_init_stream(hsmmc_t *mmc_base)
+void mmc_init_stream(struct hsmmc *mmc_base)
{
ulong start;
writel(MMC_CMD0, &mmc_base->cmd);
start = get_timer(0);
while (!(readl(&mmc_base->stat) & CC_MASK)) {
- if (get_timer(0) - start > MAX_RETRY_MS) {
- printf("%s: timedout waiting for cc!\n", __func__);
+ if (get_timer(start) > MAX_RETRY_MS) {
+ printf("%s: timeout waiting for cc!\n", __func__);
return;
}
}
;
start = get_timer(0);
while (!(readl(&mmc_base->stat) & CC_MASK)) {
- if (get_timer(0) - start > MAX_RETRY_MS) {
- printf("%s: timedout waiting for cc2!\n", __func__);
+ if (get_timer(start) > MAX_RETRY_MS) {
+ printf("%s: timeout waiting for cc2!\n", __func__);
return;
}
}
static int mmc_init_setup(struct mmc *mmc)
{
- hsmmc_t *mmc_base = (hsmmc_t *)mmc->priv;
+ struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
unsigned int reg_val;
unsigned int dsor;
ulong start;
- mmc_board_init(mmc_base);
+ mmc_board_init(mmc);
writel(readl(&mmc_base->sysconfig) | MMC_SOFTRESET,
&mmc_base->sysconfig);
start = get_timer(0);
while ((readl(&mmc_base->sysstatus) & RESETDONE) == 0) {
- if (get_timer(0) - start > MAX_RETRY_MS) {
- printf("%s: timedout waiting for cc2!\n", __func__);
+ if (get_timer(start) > MAX_RETRY_MS) {
+ printf("%s: timeout waiting for cc2!\n", __func__);
return TIMEOUT;
}
}
writel(readl(&mmc_base->sysctl) | SOFTRESETALL, &mmc_base->sysctl);
start = get_timer(0);
while ((readl(&mmc_base->sysctl) & SOFTRESETALL) != 0x0) {
- if (get_timer(0) - start > MAX_RETRY_MS) {
- printf("%s: timedout waiting for softresetall!\n",
+ if (get_timer(start) > MAX_RETRY_MS) {
+ printf("%s: timeout waiting for softresetall!\n",
__func__);
return TIMEOUT;
}
(dsor << CLKD_OFFSET) | ICE_OSCILLATE);
start = get_timer(0);
while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
- if (get_timer(0) - start > MAX_RETRY_MS) {
- printf("%s: timedout waiting for ics!\n", __func__);
+ if (get_timer(start) > MAX_RETRY_MS) {
+ printf("%s: timeout waiting for ics!\n", __func__);
return TIMEOUT;
}
}
return 0;
}
+/*
+ * MMC controller internal finite state machine reset
+ *
+ * Used to reset command or data internal state machines, using respectively
+ * SRC or SRD bit of SYSCTL register
+ */
+static void mmc_reset_controller_fsm(struct hsmmc *mmc_base, u32 bit)
+{
+ ulong start;
+
+ mmc_reg_out(&mmc_base->sysctl, bit, bit);
+
+ start = get_timer(0);
+ while ((readl(&mmc_base->sysctl) & bit) != 0) {
+ if (get_timer(0) - start > MAX_RETRY_MS) {
+ printf("%s: timedout waiting for sysctl %x to clear\n",
+ __func__, bit);
+ return;
+ }
+ }
+}
static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data)
{
- hsmmc_t *mmc_base = (hsmmc_t *)mmc->priv;
+ struct hsmmc *mmc_base = mmc->priv;
unsigned int flags, mmc_stat;
ulong start;
start = get_timer(0);
- while ((readl(&mmc_base->pstate) & DATI_MASK) == DATI_CMDDIS) {
- if (get_timer(0) - start > MAX_RETRY_MS) {
- printf("%s: timedout waiting for cmddis!\n", __func__);
+ while ((readl(&mmc_base->pstate) & (DATI_MASK | CMDI_MASK)) != 0) {
+ if (get_timer(start) > MAX_RETRY_MS) {
+ printf("%s: timeout waiting on cmd inhibit to clear\n",
+ __func__);
return TIMEOUT;
}
}
writel(0xFFFFFFFF, &mmc_base->stat);
start = get_timer(0);
while (readl(&mmc_base->stat)) {
- if (get_timer(0) - start > MAX_RETRY_MS) {
- printf("%s: timedout waiting for stat!\n", __func__);
+ if (get_timer(start) > MAX_RETRY_MS) {
+ printf("%s: timeout waiting for stat!\n", __func__);
return TIMEOUT;
}
}
start = get_timer(0);
do {
mmc_stat = readl(&mmc_base->stat);
- if (get_timer(0) - start > MAX_RETRY_MS) {
+ if (get_timer(start) > MAX_RETRY_MS) {
printf("%s : timeout: No status update\n", __func__);
return TIMEOUT;
}
} while (!mmc_stat);
- if ((mmc_stat & IE_CTO) != 0)
+ if ((mmc_stat & IE_CTO) != 0) {
+ mmc_reset_controller_fsm(mmc_base, SYSCTL_SRC);
return TIMEOUT;
- else if ((mmc_stat & ERRI_MASK) != 0)
+ } else if ((mmc_stat & ERRI_MASK) != 0)
return -1;
if (mmc_stat & CC_MASK) {
return 0;
}
-static int mmc_read_data(hsmmc_t *mmc_base, char *buf, unsigned int size)
+static int mmc_read_data(struct hsmmc *mmc_base, char *buf, unsigned int size)
{
unsigned int *output_buf = (unsigned int *)buf;
unsigned int mmc_stat;
ulong start = get_timer(0);
do {
mmc_stat = readl(&mmc_base->stat);
- if (get_timer(0) - start > MAX_RETRY_MS) {
- printf("%s: timedout waiting for status!\n",
+ if (get_timer(start) > MAX_RETRY_MS) {
+ printf("%s: timeout waiting for status!\n",
__func__);
return TIMEOUT;
}
} while (mmc_stat == 0);
+ if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
+ mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
+
if ((mmc_stat & ERRI_MASK) != 0)
return 1;
return 0;
}
-static int mmc_write_data(hsmmc_t *mmc_base, const char *buf, unsigned int size)
+static int mmc_write_data(struct hsmmc *mmc_base, const char *buf,
+ unsigned int size)
{
unsigned int *input_buf = (unsigned int *)buf;
unsigned int mmc_stat;
ulong start = get_timer(0);
do {
mmc_stat = readl(&mmc_base->stat);
- if (get_timer(0) - start > MAX_RETRY_MS) {
- printf("%s: timedout waiting for status!\n",
+ if (get_timer(start) > MAX_RETRY_MS) {
+ printf("%s: timeout waiting for status!\n",
__func__);
return TIMEOUT;
}
} while (mmc_stat == 0);
+ if ((mmc_stat & (IE_DTO | IE_DCRC | IE_DEB)) != 0)
+ mmc_reset_controller_fsm(mmc_base, SYSCTL_SRD);
+
if ((mmc_stat & ERRI_MASK) != 0)
return 1;
static void mmc_set_ios(struct mmc *mmc)
{
- hsmmc_t *mmc_base = (hsmmc_t *)mmc->priv;
+ struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv;
unsigned int dsor = 0;
ulong start;
start = get_timer(0);
while ((readl(&mmc_base->sysctl) & ICS_MASK) == ICS_NOTREADY) {
- if (get_timer(0) - start > MAX_RETRY_MS) {
- printf("%s: timedout waiting for ics!\n", __func__);
+ if (get_timer(start) > MAX_RETRY_MS) {
+ printf("%s: timeout waiting for ics!\n", __func__);
return;
}
}
writel(readl(&mmc_base->sysctl) | CEN_ENABLE, &mmc_base->sysctl);
}
-int omap_mmc_init(int dev_index)
+int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max)
{
struct mmc *mmc;
mmc->send_cmd = mmc_send_cmd;
mmc->set_ios = mmc_set_ios;
mmc->init = mmc_init_setup;
+ mmc->getcd = NULL;
switch (dev_index) {
case 0:
- mmc->priv = (hsmmc_t *)OMAP_HSMMC1_BASE;
+ mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE;
break;
+#ifdef OMAP_HSMMC2_BASE
case 1:
- mmc->priv = (hsmmc_t *)OMAP_HSMMC2_BASE;
+ mmc->priv = (struct hsmmc *)OMAP_HSMMC2_BASE;
break;
+#endif
+#ifdef OMAP_HSMMC3_BASE
case 2:
- mmc->priv = (hsmmc_t *)OMAP_HSMMC3_BASE;
+ mmc->priv = (struct hsmmc *)OMAP_HSMMC3_BASE;
break;
+#endif
default:
- mmc->priv = (hsmmc_t *)OMAP_HSMMC1_BASE;
+ mmc->priv = (struct hsmmc *)OMAP_HSMMC1_BASE;
return 1;
}
mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
- mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS;
+ mmc->host_caps = (MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS |
+ MMC_MODE_HC) & ~host_caps_mask;
mmc->f_min = 400000;
- mmc->f_max = 52000000;
+
+ if (f_max != 0)
+ mmc->f_max = f_max;
+ else {
+ if (mmc->host_caps & MMC_MODE_HS) {
+ if (mmc->host_caps & MMC_MODE_HS_52MHz)
+ mmc->f_max = 52000000;
+ else
+ mmc->f_max = 26000000;
+ } else
+ mmc->f_max = 20000000;
+ }
mmc->b_max = 0;
projects / karo-tx-uboot.git / blobdiff