netxen: refresh firmware info after reset

[mv-sheeva.git] / drivers / net / bnx2x_reg.h

diff --git a/drivers/net/bnx2x_reg.h b/drivers/net/bnx2x_reg.h
index b8ce6fc927a06631d113df0e0da5cd328647c78c..d771168ec20aa89d49ec25abaed6c71644e76b8d 100644 (file)
--- a/drivers/net/bnx2x_reg.h
+++ b/drivers/net/bnx2x_reg.h
@@ -1660,6 +1660,8 @@
 #define NIG_REG_EGRESS_PBF0_IN_EN                               0x100cc
 /* [RW 1] Input enable for TX PBF user packet port1 IF */
 #define NIG_REG_EGRESS_PBF1_IN_EN                               0x100d0
+/* [RW 1] Input enable for TX UMP management packet port0 IF */
+#define NIG_REG_EGRESS_UMP0_IN_EN                               0x100d4
 /* [RW 1] Input enable for RX_EMAC0 IF */
 #define NIG_REG_EMAC0_IN_EN                                     0x100a4
 /* [RW 1] output enable for TX EMAC pause port 0 IF */
@@ -5843,25 +5845,33 @@ Theotherbitsarereservedandshouldbezero*/
 #define MDIO_PMA_REG_ROM_VER2          0xca1a
 #define MDIO_PMA_REG_EDC_FFE_MAIN      0xca1b
 #define MDIO_PMA_REG_PLL_BANDWIDTH     0xca1d
-#define MDIO_PMA_REG_GEN_CTRL2         0xca1e
+#define MDIO_PMA_REG_PLL_CTRL          0xca1e
 #define MDIO_PMA_REG_MISC_CTRL0        0xca23
 #define MDIO_PMA_REG_LRM_MODE          0xca3f
 #define MDIO_PMA_REG_CDR_BANDWIDTH     0xca46
 #define MDIO_PMA_REG_MISC_CTRL1        0xca85
 
-#define MDIO_PMA_REG_8726_TWO_WIRE_CTRL        0x8000
-#define MDIO_PMA_REG_8726_TWO_WIRE_CTRL_STATUS_MASK    0x000c
-#define MDIO_PMA_REG_8726_TWO_WIRE_STATUS_IDLE         0x0000
-#define MDIO_PMA_REG_8726_TWO_WIRE_STATUS_COMPLETE     0x0004
-#define MDIO_PMA_REG_8726_TWO_WIRE_STATUS_IN_PROGRESS  0x0008
-#define MDIO_PMA_REG_8726_TWO_WIRE_STATUS_FAILED       0x000c
-#define MDIO_PMA_REG_8726_TWO_WIRE_BYTE_CNT    0x8002
-#define MDIO_PMA_REG_8726_TWO_WIRE_MEM_ADDR    0x8003
+#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL         0x8000
+#define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK     0x000c
+#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE          0x0000
+#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE      0x0004
+#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS   0x0008
+#define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED        0x000c
+#define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT     0x8002
+#define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR     0x8003
 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF    0xc820
 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff
 #define MDIO_PMA_REG_8726_TX_CTRL1             0xca01
 #define MDIO_PMA_REG_8726_TX_CTRL2             0xca05
 
+#define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR  0x8005
+#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF    0x8007
+#define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff
+#define MDIO_PMA_REG_8727_MISC_CTRL            0x8309
+#define MDIO_PMA_REG_8727_TX_CTRL1             0xca02
+#define MDIO_PMA_REG_8727_TX_CTRL2             0xca05
+#define MDIO_PMA_REG_8727_PCS_OPT_CTRL         0xc808
+#define MDIO_PMA_REG_8727_GPIO_CTRL            0xc80e
 
 #define MDIO_PMA_REG_8073_CHIP_REV                     0xc801
 #define MDIO_PMA_REG_8073_SPEED_LINK_STATUS            0xc820