cxgb3 - Limit multiqueue setting to msi-x

[mv-sheeva.git] / drivers / net / cxgb3 / t3_hw.c

diff --git a/drivers/net/cxgb3/t3_hw.c b/drivers/net/cxgb3/t3_hw.c
index 58a3097579f91691485849ebc9c41a1284f20435..9a0898b0dbcef2e8d214046c3ac9137de1ccfb23 100644 (file)
--- a/drivers/net/cxgb3/t3_hw.c
+++ b/drivers/net/cxgb3/t3_hw.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2003-2007 Chelsio, Inc. All rights reserved.
+ * Copyright (c) 2003-2008 Chelsio, Inc. All rights reserved.
  *
  * This software is available to you under a choice of one of two
  * licenses.  You may choose to be licensed under the terms of the GNU
@@ -407,6 +407,29 @@ int t3_phy_advertise(struct cphy *phy, unsigned int advert)
        return mdio_write(phy, 0, MII_ADVERTISE, val);
 }
 
+/**
+ *     t3_phy_advertise_fiber - set fiber PHY advertisement register
+ *     @phy: the PHY to operate on
+ *     @advert: bitmap of capabilities the PHY should advertise
+ *
+ *     Sets a fiber PHY's advertisement register to advertise the
+ *     requested capabilities.
+ */
+int t3_phy_advertise_fiber(struct cphy *phy, unsigned int advert)
+{
+       unsigned int val = 0;
+
+       if (advert & ADVERTISED_1000baseT_Half)
+               val |= ADVERTISE_1000XHALF;
+       if (advert & ADVERTISED_1000baseT_Full)
+               val |= ADVERTISE_1000XFULL;
+       if (advert & ADVERTISED_Pause)
+               val |= ADVERTISE_1000XPAUSE;
+       if (advert & ADVERTISED_Asym_Pause)
+               val |= ADVERTISE_1000XPSE_ASYM;
+       return mdio_write(phy, 0, MII_ADVERTISE, val);
+}
+
 /**
  *     t3_set_phy_speed_duplex - force PHY speed and duplex
  *     @phy: the PHY to operate on
@@ -511,7 +534,7 @@ static const struct port_type_info port_types[] = {
        { t3_vsc8211_phy_prep },
        { NULL},
        { t3_xaui_direct_phy_prep },
-       { NULL },
+       { t3_ael2005_phy_prep },
        { t3_qt2045_phy_prep },
        { t3_ael1006_phy_prep },
        { NULL },
@@ -549,7 +572,7 @@ struct t3_vpd {
        u32 pad;                /* for multiple-of-4 sizing and alignment */
 };
 
-#define EEPROM_MAX_POLL   4
+#define EEPROM_MAX_POLL   40
 #define EEPROM_STAT_ADDR  0x4000
 #define VPD_BASE          0xc00
 
@@ -1728,6 +1751,8 @@ int t3_phy_intr_handler(struct adapter *adapter)
                                t3_link_changed(adapter, i);
                        if (phy_cause & cphy_cause_fifo_error)
                                p->phy.fifo_errors++;
+                       if (phy_cause & cphy_cause_module_change)
+                               t3_os_phymod_changed(adapter, i);
                }
        }
 
@@ -3665,6 +3690,12 @@ int t3_prep_adapter(struct adapter *adapter, const struct adapter_info *ai,
                        ;
 
                pti = &port_types[adapter->params.vpd.port_type[j]];
+               if (!pti->phy_prep) {
+                       CH_ALERT(adapter, "Invalid port type index %d\n",
+                                adapter->params.vpd.port_type[j]);
+                       return -EINVAL;
+               }
+
                ret = pti->phy_prep(&p->phy, adapter, ai->phy_base_addr + j,
                                    ai->mdio_ops);
                if (ret)