* (C) Copyright 2010
* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _DW_ETH_H
#define CONFIG_MACRESET_TIMEOUT (3 * CONFIG_SYS_HZ)
#define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
-#define CONFIG_PHYRESET_TIMEOUT (3 * CONFIG_SYS_HZ)
-#define CONFIG_AUTONEG_TIMEOUT (5 * CONFIG_SYS_HZ)
struct eth_mac_regs {
u32 conf; /* 0x00 */
u32 status; /* 0x14 */
u32 opmode; /* 0x18 */
u32 intenable; /* 0x1c */
- u8 reserved[40];
+ u32 reserved1[2];
+ u32 axibus; /* 0x28 */
+ u32 reserved2[7];
u32 currhosttxdesc; /* 0x48 */
u32 currhostrxdesc; /* 0x4c */
u32 currhosttxbuffaddr; /* 0x50 */
#define DW_DMA_BASE_OFFSET (0x1000)
+/* Default DMA Burst length */
+#ifndef CONFIG_DW_GMAC_DEFAULT_DMA_PBL
+#define CONFIG_DW_GMAC_DEFAULT_DMA_PBL 8
+#endif
+
/* Bus mode register definitions */
#define FIXEDBURST (1 << 16)
#define PRIORXTX_41 (3 << 14)
#define PRIORXTX_31 (2 << 14)
#define PRIORXTX_21 (1 << 14)
#define PRIORXTX_11 (0 << 14)
-#define BURST_1 (1 << 8)
-#define BURST_2 (2 << 8)
-#define BURST_4 (4 << 8)
-#define BURST_8 (8 << 8)
-#define BURST_16 (16 << 8)
-#define BURST_32 (32 << 8)
+#define DMA_PBL (CONFIG_DW_GMAC_DEFAULT_DMA_PBL<<8)
#define RXHIGHPRIO (1 << 1)
#define DMAMAC_SRST (1 << 0)
#define RXSTART (1 << 1)
/* Descriptior related definitions */
-#define MAC_MAX_FRAME_SZ (2048)
+#define MAC_MAX_FRAME_SZ (1600)
struct dmamacdescr {
u32 txrx_status;
u32 dmamac_cntl;
void *dmamac_addr;
struct dmamacdescr *dmamac_next;
-};
+} __aligned(ARCH_DMA_MINALIGN);
/*
* txrx_status definitions
#endif
struct dw_eth_dev {
- u32 address;
- u32 speed;
- u32 duplex;
- u32 tx_currdescnum;
- u32 rx_currdescnum;
- u32 padding;
-
struct dmamacdescr tx_mac_descrtable[CONFIG_TX_DESCR_NUM];
struct dmamacdescr rx_mac_descrtable[CONFIG_RX_DESCR_NUM];
+ char txbuffs[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
+ char rxbuffs[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
- char txbuffs[TX_TOTAL_BUFSIZE];
- char rxbuffs[RX_TOTAL_BUFSIZE];
+ u32 interface;
+ u32 tx_currdescnum;
+ u32 rx_currdescnum;
struct eth_mac_regs *mac_regs_p;
struct eth_dma_regs *dma_regs_p;
-
+#ifndef CONFIG_DM_ETH
struct eth_device *dev;
-} __attribute__ ((aligned(8)));
-
-/* Speed specific definitions */
-#define SPEED_10M 1
-#define SPEED_100M 2
-#define SPEED_1000M 3
-
-/* Duplex mode specific definitions */
-#define HALF_DUPLEX 1
-#define FULL_DUPLEX 2
+#endif
+ struct phy_device *phydev;
+ struct mii_dev *bus;
+};
#endif