Merge branch 'master' of git://git.denx.de/u-boot-arm

[karo-tx-uboot.git] / drivers / net / sh_eth.h

diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h
index 9ad800e4273e106c5d59ff5fa17f23ce95517856..331c07cb5962ac1a6d7b9d4ce9319ef19a94ca50 100644 (file)
--- a/drivers/net/sh_eth.h
+++ b/drivers/net/sh_eth.h
@@ -31,6 +31,11 @@
 #define ADDR_TO_P2(addr)       (addr)
 #endif /* defined(CONFIG_SH) */
 
+/* base padding size is 16 */
+#ifndef CONFIG_SH_ETHER_ALIGNE_SIZE
+#define CONFIG_SH_ETHER_ALIGNE_SIZE 16
+#endif
+
 /* Number of supported ports */
 #define MAX_PORT_NUM   2
 
@@ -45,15 +50,16 @@
 
 /* The size of the tx descriptor is determined by how much padding is used.
    4, 20, or 52 bytes of padding can be used */
-#define TX_DESC_PADDING                4
-#define TX_DESC_SIZE           (12 + TX_DESC_PADDING)
+#define TX_DESC_PADDING        (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
+/* same as CONFIG_SH_ETHER_ALIGNE_SIZE */
+#define TX_DESC_SIZE   (12 + TX_DESC_PADDING)
 
 /* Tx descriptor. We always use 3 bytes of padding */
 struct tx_desc_s {
        volatile u32 td0;
        u32 td1;
        u32 td2;                /* Buffer start */
-       u32 padding;
+       u8 padding[TX_DESC_PADDING];    /* aligned cache line size */
 };
 
 /* There is no limitation in the number of rx descriptors */
@@ -61,15 +67,18 @@ struct tx_desc_s {
 
 /* The size of the rx descriptor is determined by how much padding is used.
    4, 20, or 52 bytes of padding can be used */
-#define RX_DESC_PADDING                4
+#define RX_DESC_PADDING        (CONFIG_SH_ETHER_ALIGNE_SIZE - 12)
+/* same as CONFIG_SH_ETHER_ALIGNE_SIZE */
 #define RX_DESC_SIZE           (12 + RX_DESC_PADDING)
+/* aligned cache line size */
+#define RX_BUF_ALIGNE_SIZE     (CONFIG_SH_ETHER_ALIGNE_SIZE > 32 ? 64 : 32)
 
 /* Rx descriptor. We always use 4 bytes of padding */
 struct rx_desc_s {
        volatile u32 rd0;
        volatile u32 rd1;
        u32 rd2;                /* Buffer start */
-       u32 padding;
+       u8 padding[TX_DESC_PADDING];    /* aligned cache line size */
 };
 
 struct sh_eth_info {
@@ -157,6 +166,7 @@ enum {
        TLFRCR,
        CERCR,
        CEECR,
+       RMIIMR, /* R8A7790 */
        MAFCR,
        RTRATE,
        CSMR,
@@ -263,6 +273,7 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
        [RMCR]  = 0x0058,
        [TFUCR] = 0x0064,
        [RFOCR] = 0x0068,
+       [RMIIMR] = 0x006C,
        [FCFTR] = 0x0070,
        [RPADIR]        = 0x0078,
        [TRIMD] = 0x007c,
@@ -276,7 +287,9 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 #if defined(CONFIG_CPU_SH7763) || defined(CONFIG_CPU_SH7734)
 #define SH_ETH_TYPE_GETHER
 #define BASE_IO_ADDR   0xfee00000
-#elif defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
+#elif defined(CONFIG_CPU_SH7757) || \
+       defined(CONFIG_CPU_SH7752) || \
+       defined(CONFIG_CPU_SH7753)
 #if defined(CONFIG_SH_ETHER_USE_GETHER)
 #define SH_ETH_TYPE_GETHER
 #define BASE_IO_ADDR   0xfee00000
@@ -290,6 +303,9 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
 #elif defined(CONFIG_R8A7740)
 #define SH_ETH_TYPE_GETHER
 #define BASE_IO_ADDR   0xE9A00000
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
+#define SH_ETH_TYPE_ETHER
+#define BASE_IO_ADDR   0xEE700200
 #endif
 
 /*
@@ -320,6 +336,14 @@ enum DMAC_M_BIT {
 #endif
 };
 
+#if CONFIG_SH_ETHER_ALIGNE_SIZE == 64
+# define EMDR_DESC EDMR_DL1
+#elif CONFIG_SH_ETHER_ALIGNE_SIZE == 32
+# define EMDR_DESC EDMR_DL0
+#elif CONFIG_SH_ETHER_ALIGNE_SIZE == 16 /* Default */
+# define EMDR_DESC 0
+#endif
+
 /* RFLR */
 #define RFLR_RFL_MIN   0x05EE  /* Recv Frame length 1518 byte */
 
@@ -334,7 +358,9 @@ enum DMAC_T_BIT {
 
 /* GECMR */
 enum GECMR_BIT {
-#if defined(CONFIG_CPU_SH7757) || defined(CONFIG_CPU_SH7752)
+#if defined(CONFIG_CPU_SH7757) || \
+       defined(CONFIG_CPU_SH7752) || \
+       defined(CONFIG_CPU_SH7753)
        GECMR_1000B = 0x20, GECMR_100B = 0x01, GECMR_10B = 0x00,
 #else
        GECMR_1000B = 0x01, GECMR_100B = 0x04, GECMR_10B = 0x00,
@@ -485,6 +511,8 @@ enum FELIC_MODE_BIT {
        ECMR_PRM = 0x00000001,
 #ifdef CONFIG_CPU_SH7724
        ECMR_RTM = 0x00000010,
+#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
+       ECMR_RTM = 0x00000004,
 #endif
 
 };