static void tg3_enable_nvram_access(struct tg3 *tp)
{
if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
- !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
+ !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
u32 nvaccess = tr32(NVRAM_ACCESS);
tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
static void tg3_disable_nvram_access(struct tg3 *tp)
{
if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
- !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
+ !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
u32 nvaccess = tr32(NVRAM_ACCESS);
tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
/* NVRAM protection for TPM */
if (nvcfg1 & (1 << 27))
- tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
+ tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
/* NVRAM protection for TPM */
if (nvcfg1 & (1 << 27)) {
- tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
+ tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
protect = 1;
}
/* NVRAM protection for TPM */
if (nvcfg1 & (1 << 27)) {
- tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
+ tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
protect = 1;
}
tg3_enable_nvram_access(tp);
if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
- !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
+ !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
tw32(NVRAM_WRITE1, 0x406);
grc_mode = tr32(GRC_MODE);