tg3: Add support for 2 new selfboot formats

[mv-sheeva.git] / drivers / net / tg3.h

diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 8a167912902b6e13449a18343b21ebf9939a91d8..ffc12b1cb388589e5af8801f0d8d807f3c5cf58b 100644 (file)
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -110,6 +110,7 @@
 #define  CHIPREV_ID_57780_A0            0x57780000
 #define  CHIPREV_ID_57780_A1            0x57780001
 #define  CHIPREV_ID_5717_A0             0x05717000
+#define  CHIPREV_ID_57765_A0            0x57785000
 #define  GET_ASIC_REV(CHIP_REV_ID)     ((CHIP_REV_ID) >> 12)
 #define   ASIC_REV_5700                         0x07
 #define   ASIC_REV_5701                         0x00
@@ -1206,14 +1207,18 @@
 #define  DEFAULT_MB_MACRX_LOW_WATER      0x00000020
 #define  DEFAULT_MB_MACRX_LOW_WATER_5705  0x00000010
 #define  DEFAULT_MB_MACRX_LOW_WATER_5906  0x00000004
+#define  DEFAULT_MB_MACRX_LOW_WATER_57765 0x0000002a
 #define  DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098
 #define  DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780 0x0000004b
+#define  DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765 0x0000007e
 #define BUFMGR_MB_HIGH_WATER           0x00004418
 #define  DEFAULT_MB_HIGH_WATER          0x00000060
 #define  DEFAULT_MB_HIGH_WATER_5705     0x00000060
 #define  DEFAULT_MB_HIGH_WATER_5906     0x00000010
+#define  DEFAULT_MB_HIGH_WATER_57765    0x000000a0
 #define  DEFAULT_MB_HIGH_WATER_JUMBO    0x0000017c
 #define  DEFAULT_MB_HIGH_WATER_JUMBO_5780 0x00000096
+#define  DEFAULT_MB_HIGH_WATER_JUMBO_57765 0x000000ea
 #define BUFMGR_RX_MB_ALLOC_REQ         0x0000441c
 #define  BUFMGR_MB_ALLOC_BIT            0x10000000
 #define BUFMGR_RX_MB_ALLOC_RESP                0x00004420
@@ -1253,6 +1258,7 @@
 #define  RDMAC_MODE_MBUF_SBD_CRPT_ENAB  0x00002000
 #define  RDMAC_MODE_FIFO_SIZE_128       0x00020000
 #define  RDMAC_MODE_FIFO_LONG_BURST     0x00030000
+#define  RDMAC_MODE_MULT_DMA_RD_DIS     0x01000000
 #define  RDMAC_MODE_IPV4_LSO_EN                 0x08000000
 #define  RDMAC_MODE_IPV6_LSO_EN                 0x10000000
 #define RDMAC_STATUS                   0x00004804
@@ -1543,6 +1549,8 @@
 #define  GRC_MODE_HOST_SENDBDS         0x00020000
 #define  GRC_MODE_NO_TX_PHDR_CSUM      0x00100000
 #define  GRC_MODE_NVRAM_WR_ENABLE      0x00200000
+#define  GRC_MODE_PCIE_TL_SEL          0x00000000
+#define  GRC_MODE_PCIE_PL_SEL          0x00400000
 #define  GRC_MODE_NO_RX_PHDR_CSUM      0x00800000
 #define  GRC_MODE_IRQ_ON_TX_CPU_ATTN   0x01000000
 #define  GRC_MODE_IRQ_ON_RX_CPU_ATTN   0x02000000
@@ -1550,7 +1558,13 @@
 #define  GRC_MODE_IRQ_ON_DMA_ATTN      0x08000000
 #define  GRC_MODE_IRQ_ON_FLOW_ATTN     0x10000000
 #define  GRC_MODE_4X_NIC_SEND_RINGS    0x20000000
+#define  GRC_MODE_PCIE_DL_SEL          0x20000000
 #define  GRC_MODE_MCAST_FRM_ENABLE     0x40000000
+#define  GRC_MODE_PCIE_HI_1K_EN                0x80000000
+#define  GRC_MODE_PCIE_PORT_MASK       (GRC_MODE_PCIE_TL_SEL | \
+                                        GRC_MODE_PCIE_PL_SEL | \
+                                        GRC_MODE_PCIE_DL_SEL | \
+                                        GRC_MODE_PCIE_HI_1K_EN)
 #define GRC_MISC_CFG                   0x00006804
 #define  GRC_MISC_CFG_CORECLK_RESET    0x00000001
 #define  GRC_MISC_CFG_PRESCALAR_MASK   0x000000fe
@@ -1804,6 +1818,11 @@
 /* 0x7e74 --> 0x8000 unused */
 
 
+/* Alternate PCIE definitions */
+#define TG3_PCIE_TLDLPL_PORT           0x00007c00
+#define TG3_PCIE_PL_LO_PHYCTL1          0x00000004
+#define TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN        0x00001000
+
 /* OTP bit definitions */
 #define TG3_OTP_AGCTGT_MASK            0x000000e0
 #define TG3_OTP_AGCTGT_SHIFT           1
@@ -1845,6 +1864,8 @@
 #define TG3_EEPROM_SB_REVISION_0       0x00000000
 #define TG3_EEPROM_SB_REVISION_2       0x00020000
 #define TG3_EEPROM_SB_REVISION_3       0x00030000
+#define TG3_EEPROM_SB_REVISION_4       0x00040000
+#define TG3_EEPROM_SB_REVISION_5       0x00050000
 #define TG3_EEPROM_MAGIC_HW            0xabcd
 #define TG3_EEPROM_MAGIC_HW_MSK                0xffff
 
@@ -1862,6 +1883,8 @@
 #define TG3_EEPROM_SB_F1R2_EDH_OFF     0x14
 #define TG3_EEPROM_SB_F1R2_MBA_OFF     0x10
 #define TG3_EEPROM_SB_F1R3_EDH_OFF     0x18
+#define TG3_EEPROM_SB_F1R4_EDH_OFF     0x1c
+#define TG3_EEPROM_SB_F1R5_EDH_OFF     0x20
 #define TG3_EEPROM_SB_EDH_MAJ_MASK     0x00000700
 #define TG3_EEPROM_SB_EDH_MAJ_SHFT     8
 #define TG3_EEPROM_SB_EDH_MIN_MASK     0x000000ff
@@ -2093,6 +2116,9 @@
 
 /* Fast Ethernet Tranceiver definitions */
 #define MII_TG3_FET_PTEST              0x17
+#define  MII_TG3_FET_PTEST_FRC_TX_LINK 0x1000
+#define  MII_TG3_FET_PTEST_FRC_TX_LOCK 0x0800
+
 #define MII_TG3_FET_TEST               0x1f
 #define  MII_TG3_FET_SHADOW_EN         0x0080
 
@@ -2682,6 +2708,7 @@ struct tg3 {
        struct net_device               *dev;
        struct pci_dev                  *pdev;
 
+       u32                             coal_now;
        u32                             msg_enable;
 
        /* begin "tx thread" cacheline section */
@@ -2700,7 +2727,7 @@ struct tg3 {
        struct vlan_group               *vlgrp;
 #endif
 
-       struct tg3_rx_prodring_set      prodring[TG3_IRQ_MAX_VECS - 1];
+       struct tg3_rx_prodring_set      prodring[TG3_IRQ_MAX_VECS];
 
 
        /* begin "everything else" cacheline(s) section */
@@ -2812,6 +2839,7 @@ struct tg3 {
 #define TG3_FLG3_40BIT_DMA_LIMIT_BUG   0x00100000
 #define TG3_FLG3_SHORT_DMA_BUG         0x00200000
 #define TG3_FLG3_USE_JUMBO_BDFLAG      0x00400000
+#define TG3_FLG3_L1PLLPD_EN            0x00800000
 
        struct timer_list               timer;
        u16                             timer_counter;
@@ -2878,7 +2906,9 @@ struct tg3 {
 #define PHY_ID_BCM5756                 0xbc050ed0
 #define PHY_ID_BCM5784                 0xbc050fa0
 #define PHY_ID_BCM5761                 0xbc050fd0
-#define PHY_ID_BCM5717                 0x5c0d8a00
+#define PHY_ID_BCM5718C                        0x5c0d8a00
+#define PHY_ID_BCM5718S                        0xbc050ff0
+#define PHY_ID_BCM57765                        0x5c0d8a40
 #define PHY_ID_BCM5906                 0xdc00ac40
 #define PHY_ID_BCM8002                 0x60010140
 #define PHY_ID_INVALID                 0xffffffff
@@ -2921,7 +2951,8 @@ struct tg3 {
         (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM5787 || \
         (X) == PHY_ID_BCM5755 || (X) == PHY_ID_BCM5756 || \
         (X) == PHY_ID_BCM5906 || (X) == PHY_ID_BCM5761 || \
-        (X) == PHY_ID_BCM5717 || (X) == PHY_ID_BCM8002)
+        (X) == PHY_ID_BCM5718C || (X) == PHY_ID_BCM5718S || \
+        (X) == PHY_ID_BCM57765 || (X) == PHY_ID_BCM8002)
 
        struct tg3_hw_stats             *hw_stats;
        dma_addr_t                      stats_mapping;