ath9k_hw: fix A-MPDU key search issues on AR9003

[karo-tx-linux.git] / drivers / net / wireless / ath / ath9k / ar9003_phy.c

diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
index a491854fa38aa7173c5b976c54da6551f4f96aa9..656d8ce251a7f243df8667f23775276648adfd83 100644 (file)
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
@@ -128,7 +128,7 @@ static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
                                            struct ath9k_channel *chan)
 {
-       u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
+       static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
        int cur_bb_spur, negative = 0, cck_spur_freq;
        int i;
 
@@ -614,7 +614,7 @@ static int ar9003_hw_process_ini(struct ath_hw *ah,
                                 channel->max_antenna_gain * 2,
                                 channel->max_power * 2,
                                 min((u32) MAX_RATE_POWER,
-                                (u32) regulatory->power_limit));
+                                (u32) regulatory->power_limit), false);
 
        return 0;
 }
@@ -747,9 +747,9 @@ static void ar9003_hw_set_diversity(struct ath_hw *ah, bool value)
 static bool ar9003_hw_ani_control(struct ath_hw *ah,
                                  enum ath9k_ani_cmd cmd, int param)
 {
-       struct ar5416AniState *aniState = ah->curani;
        struct ath_common *common = ath9k_hw_common(ah);
        struct ath9k_channel *chan = ah->curchan;
+       struct ar5416AniState *aniState = &chan->ani;
        s32 value, value2;
 
        switch (cmd & ah->ani_function) {
@@ -1005,15 +1005,13 @@ static bool ar9003_hw_ani_control(struct ath_hw *ah,
 
        ath_print(common, ATH_DBG_ANI,
                  "ANI parameters: SI=%d, ofdmWS=%s FS=%d "
-                 "MRCcck=%s listenTime=%d CC=%d listen=%d "
+                 "MRCcck=%s listenTime=%d "
                  "ofdmErrs=%d cckErrs=%d\n",
                  aniState->spurImmunityLevel,
                  !aniState->ofdmWeakSigDetectOff ? "on" : "off",
                  aniState->firstepLevel,
                  !aniState->mrcCCKOff ? "on" : "off",
                  aniState->listenTime,
-                 aniState->cycleCount,
-                 aniState->listenTime,
                  aniState->ofdmPhyErrCount,
                  aniState->cckPhyErrCount);
        return true;
@@ -1025,25 +1023,25 @@ static void ar9003_hw_do_getnf(struct ath_hw *ah,
        int16_t nf;
 
        nf = MS(REG_READ(ah, AR_PHY_CCA_0), AR_PHY_MINCCA_PWR);
-       nfarray[0] = sign_extend(nf, 9);
+       nfarray[0] = sign_extend32(nf, 8);
 
        nf = MS(REG_READ(ah, AR_PHY_CCA_1), AR_PHY_CH1_MINCCA_PWR);
-       nfarray[1] = sign_extend(nf, 9);
+       nfarray[1] = sign_extend32(nf, 8);
 
        nf = MS(REG_READ(ah, AR_PHY_CCA_2), AR_PHY_CH2_MINCCA_PWR);
-       nfarray[2] = sign_extend(nf, 9);
+       nfarray[2] = sign_extend32(nf, 8);
 
        if (!IS_CHAN_HT40(ah->curchan))
                return;
 
        nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
-       nfarray[3] = sign_extend(nf, 9);
+       nfarray[3] = sign_extend32(nf, 8);
 
        nf = MS(REG_READ(ah, AR_PHY_EXT_CCA_1), AR_PHY_CH1_EXT_MINCCA_PWR);
-       nfarray[4] = sign_extend(nf, 9);
+       nfarray[4] = sign_extend32(nf, 8);
 
        nf = MS(REG_READ(ah, AR_PHY_EXT_CCA_2), AR_PHY_CH2_EXT_MINCCA_PWR);
-       nfarray[5] = sign_extend(nf, 9);
+       nfarray[5] = sign_extend32(nf, 8);
 }
 
 static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
@@ -1067,12 +1065,9 @@ static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
        struct ath_common *common = ath9k_hw_common(ah);
        struct ath9k_channel *chan = ah->curchan;
        struct ath9k_ani_default *iniDef;
-       int index;
        u32 val;
 
-       index = ath9k_hw_get_ani_channel_idx(ah, chan);
-       aniState = &ah->ani[index];
-       ah->curani = aniState;
+       aniState = &ah->curchan->ani;
        iniDef = &aniState->iniDef;
 
        ath_print(common, ATH_DBG_ANI,
@@ -1116,14 +1111,57 @@ static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
        aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
        aniState->ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG;
        aniState->mrcCCKOff = !ATH9K_ANI_ENABLE_MRC_CCK;
+}
+
+static void ar9003_hw_set_radar_params(struct ath_hw *ah,
+                                      struct ath_hw_radar_conf *conf)
+{
+       u32 radar_0 = 0, radar_1 = 0;
 
-       aniState->cycleCount = 0;
+       if (!conf) {
+               REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
+               return;
+       }
+
+       radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
+       radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
+       radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
+       radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
+       radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
+       radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
+
+       radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
+       radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
+       radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
+       radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
+       radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
+
+       REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
+       REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
+       if (conf->ext_channel)
+               REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
+       else
+               REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
+}
+
+static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
+{
+       struct ath_hw_radar_conf *conf = &ah->radar_conf;
+
+       conf->fir_power = -28;
+       conf->radar_rssi = 0;
+       conf->pulse_height = 10;
+       conf->pulse_rssi = 24;
+       conf->pulse_inband = 8;
+       conf->pulse_maxlen = 255;
+       conf->pulse_inband_step = 12;
+       conf->radar_inband = 8;
 }
 
 void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
 {
        struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
-       const u32 ar9300_cca_regs[6] = {
+       static const u32 ar9300_cca_regs[6] = {
                AR_PHY_CCA_0,
                AR_PHY_CCA_1,
                AR_PHY_CCA_2,
@@ -1148,8 +1186,10 @@ void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
        priv_ops->ani_control = ar9003_hw_ani_control;
        priv_ops->do_getnf = ar9003_hw_do_getnf;
        priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
+       priv_ops->set_radar_params = ar9003_hw_set_radar_params;
 
        ar9003_hw_set_nf_limits(ah);
+       ar9003_hw_set_radar_conf(ah);
        memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
 }
 
@@ -1232,7 +1272,7 @@ void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
 {
        struct ath_common *common = ath9k_hw_common(ah);
-       u32 rxc_pcnt = 0, rxf_pcnt = 0, txf_pcnt = 0, status;
+       u32 status;
 
        if (likely(!(common->debug_mask & ATH_DBG_RESET)))
                return;
@@ -1261,11 +1301,12 @@ void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
                  "** BB mode: BB_gen_controls=0x%08x **\n",
                  REG_READ(ah, AR_PHY_GEN_CTRL));
 
-       if (ath9k_hw_GetMibCycleCountsPct(ah, &rxc_pcnt, &rxf_pcnt, &txf_pcnt))
+#define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles)
+       if (common->cc_survey.cycles)
                ath_print(common, ATH_DBG_RESET,
                          "** BB busy times: rx_clear=%d%%, "
                          "rx_frame=%d%%, tx_frame=%d%% **\n",
-                         rxc_pcnt, rxf_pcnt, txf_pcnt);
+                         PCT(rx_busy), PCT(rx_frame), PCT(tx_frame));
 
        ath_print(common, ATH_DBG_RESET,
                  "==== BB update: done ====\n\n");