ath9k_hw: add AR9580 support

[mv-sheeva.git] / drivers / net / wireless / ath / ath9k / hw.h

diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
index 6acd0f975ae1ebe568bb93683d4e26555b5e90ed..3aa3fb1917758cb8ff916dbc6236fb8bd9f67f08 100644 (file)
--- a/drivers/net/wireless/ath/ath9k/hw.h
+++ b/drivers/net/wireless/ath/ath9k/hw.h
@@ -45,6 +45,7 @@
 #define AR9300_DEVID_PCIE      0x0030
 #define AR9300_DEVID_AR9340    0x0031
 #define AR9300_DEVID_AR9485_PCIE 0x0032
+#define AR9300_DEVID_AR9580    0x0033
 #define AR9300_DEVID_AR9330    0x0035
 
 #define AR5416_AR9100_DEVID    0x000b
@@ -93,6 +94,12 @@
                        (_ah)->reg_ops.write_flush((_ah));      \
        } while (0)
 
+#define PR_EEP(_s, _val)                                               \
+       do {                                                            \
+               len += snprintf(buf + len, size - len, "%20s : %10d\n", \
+                               _s, (_val));                            \
+       } while (0)
+
 #define SM(_v, _f)  (((_v) << _f##_S) & _f)
 #define MS(_v, _f)  (((_v) & _f) >> _f##_S)
 #define REG_RMW_FIELD(_a, _r, _f, _v) \
@@ -219,7 +226,6 @@ struct ath9k_ops_config {
        int additional_swba_backoff;
        int ack_6mb;
        u32 cwm_ignore_extcca;
-       u8 pcie_powersave_enable;
        bool pcieSerDesWrite;
        u8 pcie_clock_req;
        u32 pcie_waen;
@@ -439,7 +445,6 @@ struct ath9k_hw_version {
        u16 phyRev;
        u16 analog5GhzRev;
        u16 analog2GhzRev;
-       u16 subsysid;
        enum ath_usb_dev usbdev;
 };
 
@@ -602,8 +607,7 @@ struct ath_hw_private_ops {
  */
 struct ath_hw_ops {
        void (*config_pci_powersave)(struct ath_hw *ah,
-                                    int restore,
-                                    int power_off);
+                                    bool power_off);
        void (*rx_enable)(struct ath_hw *ah);
        void (*set_desc_link)(void *ds, u32 link);
        bool (*calibrate)(struct ath_hw *ah,
@@ -673,6 +677,7 @@ struct ath_hw {
 
        bool sw_mgmt_crypto;
        bool is_pciexpress;
+       bool aspm_enabled;
        bool is_monitoring;
        bool need_an_top2_fixup;
        u16 tx_trig_level;
@@ -690,6 +695,7 @@ struct ath_hw {
        enum nl80211_iftype opmode;
        enum ath9k_power_mode power_mode;
 
+       s8 noise;
        struct ath9k_hw_cal_data *caldata;
        struct ath9k_pacal_info pacal_info;
        struct ar5416Stats stats;
@@ -703,6 +709,7 @@ struct ath_hw {
        u32 txdesc_interrupt_mask;
        u32 txeol_interrupt_mask;
        u32 txurn_interrupt_mask;
+       atomic_t intr_ref_cnt;
        bool chip_fullsleep;
        u32 atim_window;
 
@@ -874,6 +881,7 @@ struct ath_bus_ops {
        bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
        void (*bt_coex_prep)(struct ath_common *common);
        void (*extn_synch_en)(struct ath_common *common);
+       void (*aspm_init)(struct ath_common *common);
 };
 
 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
@@ -1029,10 +1037,6 @@ void ath9k_ani_reset(struct ath_hw *ah, bool is_scanning);
 void ath9k_hw_proc_mib_event(struct ath_hw *ah);
 void ath9k_hw_ani_monitor(struct ath_hw *ah, struct ath9k_channel *chan);
 
-#define ATH_PCIE_CAP_LINK_CTRL 0x70
-#define ATH_PCIE_CAP_LINK_L0S  1
-#define ATH_PCIE_CAP_LINK_L1   2
-
 #define ATH9K_CLOCK_RATE_CCK           22
 #define ATH9K_CLOCK_RATE_5GHZ_OFDM     40
 #define ATH9K_CLOCK_RATE_2GHZ_OFDM     44