*****************************************************************************/
#include <linux/interrupt.h>
#include <linux/debugfs.h>
+#include <linux/bitops.h>
+#include <linux/gfp.h>
#include "iwl-dev.h"
#include "iwl-trans.h"
#include "iwl-trans-int-pcie.h"
/*TODO remove uneeded includes when the transport layer tx_free will be here */
#include "iwl-agn.h"
-#include "iwl-core.h"
#include "iwl-shared.h"
static int iwl_trans_rx_alloc(struct iwl_trans *trans)
dma_unmap_page(bus(trans)->dev, rxq->pool[i].page_dma,
PAGE_SIZE << hw_params(trans).rx_page_order,
DMA_FROM_DEVICE);
- __iwl_free_pages(priv(trans), rxq->pool[i].page);
+ __free_pages(rxq->pool[i].page,
+ hw_params(trans).rx_page_order);
rxq->pool[i].page = NULL;
}
list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
rxq->rb_stts = NULL;
}
-static int iwl_trans_rx_stop(struct iwl_priv *priv)
+static int iwl_trans_rx_stop(struct iwl_trans *trans)
{
/* stop Rx DMA */
- iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
- return iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
+ iwl_write_direct32(priv(trans), FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
+ return iwl_poll_direct_bit(priv(trans), FH_MEM_RSSR_RX_STATUS_REG,
FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
}
-static inline int iwlagn_alloc_dma_ptr(struct iwl_priv *priv,
+static inline int iwlagn_alloc_dma_ptr(struct iwl_trans *trans,
struct iwl_dma_ptr *ptr, size_t size)
{
if (WARN_ON(ptr->addr))
return -EINVAL;
- ptr->addr = dma_alloc_coherent(priv->bus->dev, size,
+ ptr->addr = dma_alloc_coherent(bus(trans)->dev, size,
&ptr->dma, GFP_KERNEL);
if (!ptr->addr)
return -ENOMEM;
return 0;
}
-static inline void iwlagn_free_dma_ptr(struct iwl_priv *priv,
+static inline void iwlagn_free_dma_ptr(struct iwl_trans *trans,
struct iwl_dma_ptr *ptr)
{
if (unlikely(!ptr->addr))
return;
- dma_free_coherent(priv->bus->dev, ptr->size, ptr->addr, ptr->dma);
+ dma_free_coherent(bus(trans)->dev, ptr->size, ptr->addr, ptr->dma);
memset(ptr, 0, sizeof(*ptr));
}
-static int iwl_trans_txq_alloc(struct iwl_priv *priv, struct iwl_tx_queue *txq,
- int slots_num, u32 txq_id)
+static int iwl_trans_txq_alloc(struct iwl_trans *trans,
+ struct iwl_tx_queue *txq, int slots_num,
+ u32 txq_id)
{
- size_t tfd_sz = hw_params(priv).tfd_size * TFD_QUEUE_SIZE_MAX;
+ size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
int i;
if (WARN_ON(txq->meta || txq->cmd || txq->txb || txq->tfds))
/* Alloc driver data array and TFD circular buffer */
/* Driver private data, only for Tx (not command) queues,
* not shared with device. */
- if (txq_id != priv->shrd->cmd_queue) {
+ if (txq_id != trans->shrd->cmd_queue) {
txq->txb = kzalloc(sizeof(txq->txb[0]) *
TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
if (!txq->txb) {
- IWL_ERR(priv, "kmalloc for auxiliary BD "
+ IWL_ERR(trans, "kmalloc for auxiliary BD "
"structures failed\n");
goto error;
}
/* Circular buffer of transmit frame descriptors (TFDs),
* shared with device */
- txq->tfds = dma_alloc_coherent(priv->bus->dev, tfd_sz, &txq->q.dma_addr,
- GFP_KERNEL);
+ txq->tfds = dma_alloc_coherent(bus(trans)->dev, tfd_sz,
+ &txq->q.dma_addr, GFP_KERNEL);
if (!txq->tfds) {
- IWL_ERR(priv, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
+ IWL_ERR(trans, "dma_alloc_coherent(%zd) failed\n", tfd_sz);
goto error;
}
txq->q.id = txq_id;
}
-static int iwl_trans_txq_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
+static int iwl_trans_txq_init(struct iwl_trans *trans, struct iwl_tx_queue *txq,
int slots_num, u32 txq_id)
{
int ret;
BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
/* Initialize queue's high/low-water marks, and head/tail indexes */
- ret = iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
+ ret = iwl_queue_init(&txq->q, TFD_QUEUE_SIZE_MAX, slots_num,
txq_id);
if (ret)
return ret;
* Tell nic where to find circular buffer of Tx Frame Descriptors for
* given Tx queue, and enable the DMA channel used for that queue.
* Circular buffer (TFD queue in DRAM) physical base address */
- iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
+ iwl_write_direct32(priv(trans), FH_MEM_CBBC_QUEUE(txq_id),
txq->q.dma_addr >> 8);
return 0;
/**
* iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
*/
-static void iwl_tx_queue_unmap(struct iwl_priv *priv, int txq_id)
+static void iwl_tx_queue_unmap(struct iwl_trans *trans, int txq_id)
{
+ struct iwl_priv *priv = priv(trans);
struct iwl_tx_queue *txq = &priv->txq[txq_id];
struct iwl_queue *q = &txq->q;
while (q->write_ptr != q->read_ptr) {
/* The read_ptr needs to bound by q->n_window */
- iwlagn_txq_free_tfd(priv, txq, get_cmd_index(q, q->read_ptr));
+ iwlagn_txq_free_tfd(trans, txq, get_cmd_index(q, q->read_ptr));
q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
}
}
* Free all buffers.
* 0-fill, but do not free "txq" descriptor structure.
*/
-static void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id)
+static void iwl_tx_queue_free(struct iwl_trans *trans, int txq_id)
{
+ struct iwl_priv *priv = priv(trans);
struct iwl_tx_queue *txq = &priv->txq[txq_id];
- struct device *dev = priv->bus->dev;
+ struct device *dev = bus(trans)->dev;
int i;
if (WARN_ON(!txq))
return;
- iwl_tx_queue_unmap(priv, txq_id);
+ iwl_tx_queue_unmap(trans, txq_id);
/* De-alloc array of command/tx buffers */
for (i = 0; i < txq->q.n_window; i++)
/* De-alloc circular buffer of TFDs */
if (txq->q.n_bd) {
- dma_free_coherent(dev, hw_params(priv).tfd_size *
+ dma_free_coherent(dev, sizeof(struct iwl_tfd) *
txq->q.n_bd, txq->tfds, txq->q.dma_addr);
memset(&txq->q.dma_addr, 0, sizeof(txq->q.dma_addr));
}
*
* Destroy all TX DMA queues and structures
*/
-static void iwl_trans_pcie_tx_free(struct iwl_priv *priv)
+static void iwl_trans_pcie_tx_free(struct iwl_trans *trans)
{
int txq_id;
+ struct iwl_trans_pcie *trans_pcie =
+ IWL_TRANS_GET_PCIE_TRANS(trans);
+ struct iwl_priv *priv = priv(trans);
/* Tx queues */
if (priv->txq) {
for (txq_id = 0;
- txq_id < hw_params(priv).max_txq_num; txq_id++)
- iwl_tx_queue_free(priv, txq_id);
+ txq_id < hw_params(trans).max_txq_num; txq_id++)
+ iwl_tx_queue_free(trans, txq_id);
}
kfree(priv->txq);
priv->txq = NULL;
- iwlagn_free_dma_ptr(priv, &priv->kw);
+ iwlagn_free_dma_ptr(trans, &trans_pcie->kw);
- iwlagn_free_dma_ptr(priv, &priv->scd_bc_tbls);
+ iwlagn_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
}
/**
* @param priv
* @return error code
*/
-static int iwl_trans_tx_alloc(struct iwl_priv *priv)
+static int iwl_trans_tx_alloc(struct iwl_trans *trans)
{
int ret;
int txq_id, slots_num;
+ struct iwl_priv *priv = priv(trans);
+ struct iwl_trans_pcie *trans_pcie =
+ IWL_TRANS_GET_PCIE_TRANS(trans);
+
+ u16 scd_bc_tbls_size = priv->cfg->base_params->num_of_queues *
+ sizeof(struct iwlagn_scd_bc_tbl);
/*It is not allowed to alloc twice, so warn when this happens.
* We cannot rely on the previous allocation, so free and fail */
goto error;
}
- ret = iwlagn_alloc_dma_ptr(priv, &priv->scd_bc_tbls,
- hw_params(priv).scd_bc_tbls_size);
+ ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
+ scd_bc_tbls_size);
if (ret) {
- IWL_ERR(priv, "Scheduler BC Table allocation failed\n");
+ IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
goto error;
}
/* Alloc keep-warm buffer */
- ret = iwlagn_alloc_dma_ptr(priv, &priv->kw, IWL_KW_SIZE);
+ ret = iwlagn_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
if (ret) {
- IWL_ERR(priv, "Keep Warm allocation failed\n");
+ IWL_ERR(trans, "Keep Warm allocation failed\n");
goto error;
}
priv->txq = kzalloc(sizeof(struct iwl_tx_queue) *
priv->cfg->base_params->num_of_queues, GFP_KERNEL);
if (!priv->txq) {
- IWL_ERR(priv, "Not enough memory for txq\n");
+ IWL_ERR(trans, "Not enough memory for txq\n");
ret = ENOMEM;
goto error;
}
/* Alloc and init all Tx queues, including the command queue (#4/#9) */
- for (txq_id = 0; txq_id < hw_params(priv).max_txq_num; txq_id++) {
- slots_num = (txq_id == priv->shrd->cmd_queue) ?
+ for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
+ slots_num = (txq_id == trans->shrd->cmd_queue) ?
TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
- ret = iwl_trans_txq_alloc(priv, &priv->txq[txq_id], slots_num,
+ ret = iwl_trans_txq_alloc(trans, &priv->txq[txq_id], slots_num,
txq_id);
if (ret) {
- IWL_ERR(priv, "Tx %d queue alloc failed\n", txq_id);
+ IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
goto error;
}
}
return 0;
error:
- iwl_trans_tx_free(trans(priv));
+ iwl_trans_tx_free(trans);
return ret;
}
-static int iwl_tx_init(struct iwl_priv *priv)
+static int iwl_tx_init(struct iwl_trans *trans)
{
int ret;
int txq_id, slots_num;
unsigned long flags;
bool alloc = false;
+ struct iwl_priv *priv = priv(trans);
+ struct iwl_trans_pcie *trans_pcie =
+ IWL_TRANS_GET_PCIE_TRANS(trans);
if (!priv->txq) {
- ret = iwl_trans_tx_alloc(priv);
+ ret = iwl_trans_tx_alloc(trans);
if (ret)
goto error;
alloc = true;
}
- spin_lock_irqsave(&priv->shrd->lock, flags);
+ spin_lock_irqsave(&trans->shrd->lock, flags);
/* Turn off all Tx DMA fifos */
iwl_write_prph(priv, SCD_TXFACT, 0);
/* Tell NIC where to find the "keep warm" buffer */
- iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4);
+ iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, trans_pcie->kw.dma >> 4);
- spin_unlock_irqrestore(&priv->shrd->lock, flags);
+ spin_unlock_irqrestore(&trans->shrd->lock, flags);
/* Alloc and init all Tx queues, including the command queue (#4/#9) */
- for (txq_id = 0; txq_id < hw_params(priv).max_txq_num; txq_id++) {
- slots_num = (txq_id == priv->shrd->cmd_queue) ?
+ for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++) {
+ slots_num = (txq_id == trans->shrd->cmd_queue) ?
TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
- ret = iwl_trans_txq_init(priv, &priv->txq[txq_id], slots_num,
+ ret = iwl_trans_txq_init(trans, &priv->txq[txq_id], slots_num,
txq_id);
if (ret) {
- IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
+ IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
goto error;
}
}
error:
/*Upon error, free only if we allocated something */
if (alloc)
- iwl_trans_tx_free(trans(priv));
+ iwl_trans_tx_free(trans);
return ret;
}
~APMG_PS_CTRL_MSK_PWR_SRC);
}
-static int iwl_nic_init(struct iwl_priv *priv)
+static int iwl_nic_init(struct iwl_trans *trans)
{
unsigned long flags;
+ struct iwl_priv *priv = priv(trans);
/* nic_init */
- spin_lock_irqsave(&priv->shrd->lock, flags);
+ spin_lock_irqsave(&trans->shrd->lock, flags);
iwl_apm_init(priv);
/* Set interrupt coalescing calibration timer to default (512 usecs) */
iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
- spin_unlock_irqrestore(&priv->shrd->lock, flags);
+ spin_unlock_irqrestore(&trans->shrd->lock, flags);
iwl_set_pwr_vmain(priv);
priv->cfg->lib->nic_config(priv);
/* Allocate the RX queue, or reset if it is already allocated */
- iwl_rx_init(trans(priv));
+ iwl_rx_init(trans);
/* Allocate or reset and init all Tx and Command queues */
- if (iwl_tx_init(priv))
+ if (iwl_tx_init(trans))
return -ENOMEM;
if (priv->cfg->base_params->shadow_reg_enable) {
0x800FFFFF);
}
- set_bit(STATUS_INIT, &priv->shrd->status);
+ set_bit(STATUS_INIT, &trans->shrd->status);
return 0;
}
#define HW_READY_TIMEOUT (50)
/* Note: returns poll_bit return value, which is >= 0 if success */
-static int iwl_set_hw_ready(struct iwl_priv *priv)
+static int iwl_set_hw_ready(struct iwl_trans *trans)
{
int ret;
- iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
+ iwl_set_bit(priv(trans), CSR_HW_IF_CONFIG_REG,
CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
/* See if we got it */
- ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
+ ret = iwl_poll_bit(priv(trans), CSR_HW_IF_CONFIG_REG,
CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
HW_READY_TIMEOUT);
- IWL_DEBUG_INFO(priv, "hardware%s ready\n", ret < 0 ? " not" : "");
+ IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
return ret;
}
/* Note: returns standard 0/-ERROR code */
-static int iwl_trans_pcie_prepare_card_hw(struct iwl_priv *priv)
+static int iwl_trans_pcie_prepare_card_hw(struct iwl_trans *trans)
{
int ret;
- IWL_DEBUG_INFO(priv, "iwl_trans_prepare_card_hw enter\n");
+ IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
- ret = iwl_set_hw_ready(priv);
+ ret = iwl_set_hw_ready(trans);
if (ret >= 0)
return 0;
/* If HW is not ready, prepare the conditions to check again */
- iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
+ iwl_set_bit(priv(trans), CSR_HW_IF_CONFIG_REG,
CSR_HW_IF_CONFIG_REG_PREPARE);
- ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
+ ret = iwl_poll_bit(priv(trans), CSR_HW_IF_CONFIG_REG,
~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
return ret;
/* HW should be ready by now, check again. */
- ret = iwl_set_hw_ready(priv);
+ ret = iwl_set_hw_ready(trans);
if (ret >= 0)
return 0;
return ret;
}
-static int iwl_trans_pcie_start_device(struct iwl_priv *priv)
+static int iwl_trans_pcie_start_device(struct iwl_trans *trans)
{
int ret;
+ struct iwl_priv *priv = priv(trans);
priv->ucode_owner = IWL_OWNERSHIP_DRIVER;
if ((priv->cfg->sku & EEPROM_SKU_CAP_AMT_ENABLE) &&
- iwl_trans_pcie_prepare_card_hw(priv)) {
- IWL_WARN(priv, "Exit HW not ready\n");
+ iwl_trans_pcie_prepare_card_hw(trans)) {
+ IWL_WARN(trans, "Exit HW not ready\n");
return -EIO;
}
/* If platform's RF_KILL switch is NOT set to KILL */
if (iwl_read32(priv, CSR_GP_CNTRL) &
CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
- clear_bit(STATUS_RF_KILL_HW, &priv->shrd->status);
+ clear_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
else
- set_bit(STATUS_RF_KILL_HW, &priv->shrd->status);
+ set_bit(STATUS_RF_KILL_HW, &trans->shrd->status);
- if (iwl_is_rfkill(priv)) {
+ if (iwl_is_rfkill(trans->shrd)) {
wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
- iwl_enable_interrupts(trans(priv));
+ iwl_enable_interrupts(trans);
return -ERFKILL;
}
iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
- ret = iwl_nic_init(priv);
+ ret = iwl_nic_init(trans);
if (ret) {
- IWL_ERR(priv, "Unable to init nic\n");
+ IWL_ERR(trans, "Unable to init nic\n");
return ret;
}
/* clear (again), then enable host interrupts */
iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
- iwl_enable_interrupts(trans(priv));
+ iwl_enable_interrupts(trans);
/* really make sure rfkill handshake bits are cleared */
iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
* Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
* must be called under priv->shrd->lock and mac access
*/
-static void iwl_trans_txq_set_sched(struct iwl_priv *priv, u32 mask)
+static void iwl_trans_txq_set_sched(struct iwl_trans *trans, u32 mask)
{
- iwl_write_prph(priv, SCD_TXFACT, mask);
+ iwl_write_prph(priv(trans), SCD_TXFACT, mask);
}
#define IWL_AC_UNSET -1
{ IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
{ IWL_TX_FIFO_AUX, IWL_AC_UNSET, },
};
-static void iwl_trans_pcie_tx_start(struct iwl_priv *priv)
+static void iwl_trans_pcie_tx_start(struct iwl_trans *trans)
{
const struct queue_to_fifo_ac *queue_to_fifo;
struct iwl_rxon_context *ctx;
+ struct iwl_priv *priv = priv(trans);
+ struct iwl_trans_pcie *trans_pcie =
+ IWL_TRANS_GET_PCIE_TRANS(trans);
u32 a;
unsigned long flags;
int i, chan;
u32 reg_val;
- spin_lock_irqsave(&priv->shrd->lock, flags);
+ spin_lock_irqsave(&trans->shrd->lock, flags);
- priv->scd_base_addr = iwl_read_prph(priv, SCD_SRAM_BASE_ADDR);
- a = priv->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
+ trans_pcie->scd_base_addr = iwl_read_prph(priv, SCD_SRAM_BASE_ADDR);
+ a = trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_LOWER_BOUND;
/* reset conext data memory */
- for (; a < priv->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
+ for (; a < trans_pcie->scd_base_addr + SCD_CONTEXT_MEM_UPPER_BOUND;
a += 4)
iwl_write_targ_mem(priv, a, 0);
/* reset tx status memory */
- for (; a < priv->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
+ for (; a < trans_pcie->scd_base_addr + SCD_TX_STTS_MEM_UPPER_BOUND;
a += 4)
iwl_write_targ_mem(priv, a, 0);
- for (; a < priv->scd_base_addr +
+ for (; a < trans_pcie->scd_base_addr +
SCD_TRANS_TBL_OFFSET_QUEUE(hw_params(priv).max_txq_num);
a += 4)
iwl_write_targ_mem(priv, a, 0);
iwl_write_prph(priv, SCD_DRAM_BASE_ADDR,
- priv->scd_bc_tbls.dma >> 10);
+ trans_pcie->scd_bc_tbls.dma >> 10);
/* Enable DMA channel */
for (chan = 0; chan < FH_TCSR_CHNL_NUM ; chan++)
for (i = 0; i < hw_params(priv).max_txq_num; i++) {
iwl_write_prph(priv, SCD_QUEUE_RDPTR(i), 0);
iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
- iwl_write_targ_mem(priv, priv->scd_base_addr +
+ iwl_write_targ_mem(priv, trans_pcie->scd_base_addr +
SCD_CONTEXT_QUEUE_OFFSET(i), 0);
- iwl_write_targ_mem(priv, priv->scd_base_addr +
+ iwl_write_targ_mem(priv, trans_pcie->scd_base_addr +
SCD_CONTEXT_QUEUE_OFFSET(i) +
sizeof(u32),
((SCD_WIN_SIZE <<
}
iwl_write_prph(priv, SCD_INTERRUPT_MASK,
- IWL_MASK(0, hw_params(priv).max_txq_num));
+ IWL_MASK(0, hw_params(trans).max_txq_num));
/* Activate all Tx DMA/FIFO channels */
- iwl_trans_txq_set_sched(priv, IWL_MASK(0, 7));
+ iwl_trans_txq_set_sched(trans, IWL_MASK(0, 7));
/* map queues to FIFOs */
if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
else
queue_to_fifo = iwlagn_default_queue_to_tx_fifo;
- iwl_trans_set_wr_ptrs(priv, priv->shrd->cmd_queue, 0);
+ iwl_trans_set_wr_ptrs(trans, trans->shrd->cmd_queue, 0);
/* make sure all queue are not stopped */
memset(&priv->queue_stopped[0], 0, sizeof(priv->queue_stopped));
/* reset to 0 to enable all the queue first */
priv->txq_ctx_active_msk = 0;
- BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) !=
+ BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) <
IWLAGN_FIRST_AMPDU_QUEUE);
- BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) !=
+ BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) <
IWLAGN_FIRST_AMPDU_QUEUE);
for (i = 0; i < IWLAGN_FIRST_AMPDU_QUEUE; i++) {
iwl_trans_tx_queue_set_status(priv, &priv->txq[i], fifo, 0);
}
- spin_unlock_irqrestore(&priv->shrd->lock, flags);
+ spin_unlock_irqrestore(&trans->shrd->lock, flags);
/* Enable L1-Active */
iwl_clear_bits_prph(priv, APMG_PCIDEV_STT_REG,
/**
* iwlagn_txq_ctx_stop - Stop all Tx DMA channels
*/
-static int iwl_trans_tx_stop(struct iwl_priv *priv)
+static int iwl_trans_tx_stop(struct iwl_trans *trans)
{
int ch, txq_id;
unsigned long flags;
+ struct iwl_priv *priv = priv(trans);
/* Turn off all Tx DMA fifos */
- spin_lock_irqsave(&priv->shrd->lock, flags);
+ spin_lock_irqsave(&trans->shrd->lock, flags);
- iwl_trans_txq_set_sched(priv, 0);
+ iwl_trans_txq_set_sched(trans, 0);
/* Stop each Tx DMA channel, and wait for it to be idle */
for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
- iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
- if (iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
+ iwl_write_direct32(priv(trans),
+ FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
+ if (iwl_poll_direct_bit(priv(trans), FH_TSSR_TX_STATUS_REG,
FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
1000))
- IWL_ERR(priv, "Failing on timeout while stopping"
+ IWL_ERR(trans, "Failing on timeout while stopping"
" DMA channel %d [0x%08x]", ch,
- iwl_read_direct32(priv, FH_TSSR_TX_STATUS_REG));
+ iwl_read_direct32(priv(trans),
+ FH_TSSR_TX_STATUS_REG));
}
- spin_unlock_irqrestore(&priv->shrd->lock, flags);
+ spin_unlock_irqrestore(&trans->shrd->lock, flags);
if (!priv->txq) {
- IWL_WARN(priv, "Stopping tx queues that aren't allocated...");
+ IWL_WARN(trans, "Stopping tx queues that aren't allocated...");
return 0;
}
/* Unmap DMA from host system and free skb's */
- for (txq_id = 0; txq_id < hw_params(priv).max_txq_num; txq_id++)
- iwl_tx_queue_unmap(priv, txq_id);
+ for (txq_id = 0; txq_id < hw_params(trans).max_txq_num; txq_id++)
+ iwl_tx_queue_unmap(trans, txq_id);
return 0;
}
-static void iwl_trans_pcie_stop_device(struct iwl_priv *priv)
+static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
{
/* stop and reset the on-board processor */
- iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
+ iwl_write32(priv(trans), CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
/* tell the device to stop sending interrupts */
- iwl_trans_disable_sync_irq(trans(priv));
+ iwl_trans_disable_sync_irq(trans);
/* device going down, Stop using ICT table */
- iwl_disable_ict(trans(priv));
+ iwl_disable_ict(trans);
/*
* If a HW restart happens during firmware loading,
* restart. So don't process again if the device is
* already dead.
*/
- if (test_bit(STATUS_DEVICE_ENABLED, &priv->shrd->status)) {
- iwl_trans_tx_stop(priv);
- iwl_trans_rx_stop(priv);
+ if (test_bit(STATUS_DEVICE_ENABLED, &trans->shrd->status)) {
+ iwl_trans_tx_stop(trans);
+ iwl_trans_rx_stop(trans);
/* Power-down device's busmaster DMA clocks */
- iwl_write_prph(priv, APMG_CLK_DIS_REG,
+ iwl_write_prph(priv(trans), APMG_CLK_DIS_REG,
APMG_CLK_VAL_DMA_CLK_RQT);
udelay(5);
}
/* Make sure (redundant) we've released our request to stay awake */
- iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
+ iwl_clear_bit(priv(trans), CSR_GP_CNTRL,
+ CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
/* Stop the device, and put it in low power state */
- iwl_apm_stop(priv);
+ iwl_apm_stop(priv(trans));
}
-static struct iwl_tx_cmd *iwl_trans_pcie_get_tx_cmd(struct iwl_priv *priv,
+static struct iwl_tx_cmd *iwl_trans_pcie_get_tx_cmd(struct iwl_trans *trans,
int txq_id)
{
+ struct iwl_priv *priv = priv(trans);
struct iwl_tx_queue *txq = &priv->txq[txq_id];
struct iwl_queue *q = &txq->q;
struct iwl_device_cmd *dev_cmd;
}
/* Attach buffers to TFD */
- iwlagn_txq_attach_buf_to_tfd(priv, txq, txcmd_phys, firstlen, 1);
+ iwlagn_txq_attach_buf_to_tfd(trans(priv), txq, txcmd_phys,
+ firstlen, 1);
if (secondlen > 0)
- iwlagn_txq_attach_buf_to_tfd(priv, txq, phys_addr,
+ iwlagn_txq_attach_buf_to_tfd(trans(priv), txq, phys_addr,
secondlen, 0);
scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
/* Set up entry for this TFD in Tx byte-count array */
if (ampdu)
- iwl_trans_txq_update_byte_cnt_tbl(priv, txq,
+ iwl_trans_txq_update_byte_cnt_tbl(trans(priv), txq,
le16_to_cpu(tx_cmd->len));
dma_sync_single_for_device(priv->bus->dev, txcmd_phys, firstlen,
* regardless of the value of ret. "ret" only indicates
* whether or not we should update the write pointer.
*/
- if ((iwl_queue_space(q) < q->high_mark) && priv->mac80211_registered) {
+ if (iwl_queue_space(q) < q->high_mark) {
if (wait_write_ptr) {
txq->need_update = 1;
iwl_txq_update_write_ptr(priv, txq);
return 0;
}
-static void iwl_trans_pcie_kick_nic(struct iwl_priv *priv)
+static void iwl_trans_pcie_kick_nic(struct iwl_trans *trans)
{
/* Remove all resets to allow NIC to operate */
- iwl_write32(priv, CSR_RESET, 0);
+ iwl_write32(priv(trans), CSR_RESET, 0);
}
static int iwl_trans_pcie_request_irq(struct iwl_trans *trans)
return 0;
}
+static void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id,
+ int ssn, u32 status, struct sk_buff_head *skbs)
+{
+ struct iwl_priv *priv = priv(trans);
+ struct iwl_tx_queue *txq = &priv->txq[txq_id];
+ /* n_bd is usually 256 => n_bd - 1 = 0xff */
+ int tfd_num = ssn & (txq->q.n_bd - 1);
+ u8 agg_state;
+ bool cond;
+
+ if (txq->sched_retry) {
+ agg_state =
+ priv->stations[txq->sta_id].tid[txq->tid].agg.state;
+ cond = (agg_state != IWL_EMPTYING_HW_QUEUE_DELBA);
+ } else {
+ cond = (status != TX_STATUS_FAIL_PASSIVE_NO_RX);
+ }
+
+ if (txq->q.read_ptr != tfd_num) {
+ IWL_DEBUG_TX_REPLY(trans, "Retry scheduler reclaim "
+ "scd_ssn=%d idx=%d txq=%d swq=%d\n",
+ ssn , tfd_num, txq_id, txq->swq_id);
+ iwl_tx_queue_reclaim(trans, txq_id, tfd_num, skbs);
+ if (iwl_queue_space(&txq->q) > txq->q.low_mark && cond)
+ iwl_wake_queue(priv, txq);
+ }
+}
+
static void iwl_trans_pcie_disable_sync_irq(struct iwl_trans *trans)
{
unsigned long flags;
tasklet_kill(&trans_pcie->irq_tasklet);
}
-static void iwl_trans_pcie_free(struct iwl_priv *priv)
+static void iwl_trans_pcie_free(struct iwl_trans *trans)
{
- free_irq(priv->bus->irq, trans(priv));
- iwl_free_isr_ict(trans(priv));
- kfree(trans(priv));
- trans(priv) = NULL;
+ free_irq(bus(trans)->irq, trans);
+ iwl_free_isr_ict(trans);
+ trans->shrd->trans = NULL;
+ kfree(trans);
}
#ifdef CONFIG_PM
iwl_trans->ops = &trans_ops_pcie;
iwl_trans->shrd = shrd;
trans_pcie->trans = iwl_trans;
+ spin_lock_init(&iwl_trans->hcmd_lock);
}
return iwl_trans;
.llseek = generic_file_llseek, \
};
+#define DEBUGFS_WRITE_FILE_OPS(name) \
+ DEBUGFS_WRITE_FUNC(name); \
+static const struct file_operations iwl_dbgfs_##name##_ops = { \
+ .write = iwl_dbgfs_##name##_write, \
+ .open = iwl_dbgfs_open_file_generic, \
+ .llseek = generic_file_llseek, \
+};
+
#define DEBUGFS_READ_WRITE_FILE_OPS(name) \
DEBUGFS_READ_FUNC(name); \
DEBUGFS_WRITE_FUNC(name); \
int pos = 0;
ssize_t ret = -ENOMEM;
- ret = pos = iwl_dump_nic_event_log(priv(trans), true, &buf, true);
+ ret = pos = iwl_dump_nic_event_log(trans, true, &buf, true);
if (buf) {
ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
kfree(buf);
if (sscanf(buf, "%d", &event_log_flag) != 1)
return -EFAULT;
if (event_log_flag == 1)
- iwl_dump_nic_event_log(priv(trans), true, NULL, false);
+ iwl_dump_nic_event_log(trans, true, NULL, false);
return count;
}
return count;
}
+static const char *get_csr_string(int cmd)
+{
+ switch (cmd) {
+ IWL_CMD(CSR_HW_IF_CONFIG_REG);
+ IWL_CMD(CSR_INT_COALESCING);
+ IWL_CMD(CSR_INT);
+ IWL_CMD(CSR_INT_MASK);
+ IWL_CMD(CSR_FH_INT_STATUS);
+ IWL_CMD(CSR_GPIO_IN);
+ IWL_CMD(CSR_RESET);
+ IWL_CMD(CSR_GP_CNTRL);
+ IWL_CMD(CSR_HW_REV);
+ IWL_CMD(CSR_EEPROM_REG);
+ IWL_CMD(CSR_EEPROM_GP);
+ IWL_CMD(CSR_OTP_GP_REG);
+ IWL_CMD(CSR_GIO_REG);
+ IWL_CMD(CSR_GP_UCODE_REG);
+ IWL_CMD(CSR_GP_DRIVER_REG);
+ IWL_CMD(CSR_UCODE_DRV_GP1);
+ IWL_CMD(CSR_UCODE_DRV_GP2);
+ IWL_CMD(CSR_LED_REG);
+ IWL_CMD(CSR_DRAM_INT_TBL_REG);
+ IWL_CMD(CSR_GIO_CHICKEN_BITS);
+ IWL_CMD(CSR_ANA_PLL_CFG);
+ IWL_CMD(CSR_HW_REV_WA_REG);
+ IWL_CMD(CSR_DBG_HPET_MEM_REG);
+ default:
+ return "UNKNOWN";
+ }
+}
+
+void iwl_dump_csr(struct iwl_trans *trans)
+{
+ int i;
+ static const u32 csr_tbl[] = {
+ CSR_HW_IF_CONFIG_REG,
+ CSR_INT_COALESCING,
+ CSR_INT,
+ CSR_INT_MASK,
+ CSR_FH_INT_STATUS,
+ CSR_GPIO_IN,
+ CSR_RESET,
+ CSR_GP_CNTRL,
+ CSR_HW_REV,
+ CSR_EEPROM_REG,
+ CSR_EEPROM_GP,
+ CSR_OTP_GP_REG,
+ CSR_GIO_REG,
+ CSR_GP_UCODE_REG,
+ CSR_GP_DRIVER_REG,
+ CSR_UCODE_DRV_GP1,
+ CSR_UCODE_DRV_GP2,
+ CSR_LED_REG,
+ CSR_DRAM_INT_TBL_REG,
+ CSR_GIO_CHICKEN_BITS,
+ CSR_ANA_PLL_CFG,
+ CSR_HW_REV_WA_REG,
+ CSR_DBG_HPET_MEM_REG
+ };
+ IWL_ERR(trans, "CSR values:\n");
+ IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
+ "CSR_INT_PERIODIC_REG)\n");
+ for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
+ IWL_ERR(trans, " %25s: 0X%08x\n",
+ get_csr_string(csr_tbl[i]),
+ iwl_read32(priv(trans), csr_tbl[i]));
+ }
+}
+
+static ssize_t iwl_dbgfs_csr_write(struct file *file,
+ const char __user *user_buf,
+ size_t count, loff_t *ppos)
+{
+ struct iwl_trans *trans = file->private_data;
+ char buf[8];
+ int buf_size;
+ int csr;
+
+ memset(buf, 0, sizeof(buf));
+ buf_size = min(count, sizeof(buf) - 1);
+ if (copy_from_user(buf, user_buf, buf_size))
+ return -EFAULT;
+ if (sscanf(buf, "%d", &csr) != 1)
+ return -EFAULT;
+
+ iwl_dump_csr(trans);
+
+ return count;
+}
+
+static const char *get_fh_string(int cmd)
+{
+ switch (cmd) {
+ IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
+ IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
+ IWL_CMD(FH_RSCSR_CHNL0_WPTR);
+ IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
+ IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
+ IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
+ IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
+ IWL_CMD(FH_TSSR_TX_STATUS_REG);
+ IWL_CMD(FH_TSSR_TX_ERROR_REG);
+ default:
+ return "UNKNOWN";
+ }
+}
+
+int iwl_dump_fh(struct iwl_trans *trans, char **buf, bool display)
+{
+ int i;
+#ifdef CONFIG_IWLWIFI_DEBUG
+ int pos = 0;
+ size_t bufsz = 0;
+#endif
+ static const u32 fh_tbl[] = {
+ FH_RSCSR_CHNL0_STTS_WPTR_REG,
+ FH_RSCSR_CHNL0_RBDCB_BASE_REG,
+ FH_RSCSR_CHNL0_WPTR,
+ FH_MEM_RCSR_CHNL0_CONFIG_REG,
+ FH_MEM_RSSR_SHARED_CTRL_REG,
+ FH_MEM_RSSR_RX_STATUS_REG,
+ FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
+ FH_TSSR_TX_STATUS_REG,
+ FH_TSSR_TX_ERROR_REG
+ };
+#ifdef CONFIG_IWLWIFI_DEBUG
+ if (display) {
+ bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
+ *buf = kmalloc(bufsz, GFP_KERNEL);
+ if (!*buf)
+ return -ENOMEM;
+ pos += scnprintf(*buf + pos, bufsz - pos,
+ "FH register values:\n");
+ for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
+ pos += scnprintf(*buf + pos, bufsz - pos,
+ " %34s: 0X%08x\n",
+ get_fh_string(fh_tbl[i]),
+ iwl_read_direct32(priv(trans), fh_tbl[i]));
+ }
+ return pos;
+ }
+#endif
+ IWL_ERR(trans, "FH register values:\n");
+ for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
+ IWL_ERR(trans, " %34s: 0X%08x\n",
+ get_fh_string(fh_tbl[i]),
+ iwl_read_direct32(priv(trans), fh_tbl[i]));
+ }
+ return 0;
+}
+
+static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
+ char __user *user_buf,
+ size_t count, loff_t *ppos)
+{
+ struct iwl_trans *trans = file->private_data;
+ char *buf;
+ int pos = 0;
+ ssize_t ret = -EFAULT;
+
+ ret = pos = iwl_dump_fh(trans, &buf, true);
+ if (buf) {
+ ret = simple_read_from_buffer(user_buf,
+ count, ppos, buf, pos);
+ kfree(buf);
+ }
+
+ return ret;
+}
+
DEBUGFS_READ_WRITE_FILE_OPS(traffic_log);
DEBUGFS_READ_WRITE_FILE_OPS(log_event);
DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
+DEBUGFS_READ_FILE_OPS(fh_reg);
DEBUGFS_READ_FILE_OPS(rx_queue);
DEBUGFS_READ_FILE_OPS(tx_queue);
+DEBUGFS_WRITE_FILE_OPS(csr);
/*
* Create the debugfs files and directories
DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
DEBUGFS_ADD_FILE(log_event, dir, S_IWUSR | S_IRUSR);
DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
+ DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
+ DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
return 0;
}
#else
.get_tx_cmd = iwl_trans_pcie_get_tx_cmd,
.tx = iwl_trans_pcie_tx,
+ .reclaim = iwl_trans_pcie_reclaim,
.txq_agg_disable = iwl_trans_pcie_txq_agg_disable,
.txq_agg_setup = iwl_trans_pcie_txq_agg_setup,
projects / karo-tx-linux.git / blobdiff