Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/sage/ceph...

[karo-tx-linux.git] / drivers / pci / host / Kconfig

diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index 90f5ccacce4ba819786506054deec71f05473026..c4b6568e486dfb464ca1cbf786ca26f4e5fcbab2 100644 (file)
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -32,7 +32,10 @@ config PCI_IMX6
 
 config PCI_TEGRA
        bool "NVIDIA Tegra PCIe controller"
-       depends on ARCH_TEGRA
+       depends on ARCH_TEGRA && !ARM64
+       help
+         Say Y here if you want support for the PCIe host controller found
+         on NVIDIA Tegra SoCs.
 
 config PCI_RCAR_GEN2
        bool "Renesas R-Car Gen2 Internal PCI controller"
@@ -63,4 +66,40 @@ config PCIE_SPEAR13XX
        help
          Say Y here if you want PCIe support on SPEAr13XX SoCs.
 
+config PCI_KEYSTONE
+       bool "TI Keystone PCIe controller"
+       depends on ARCH_KEYSTONE
+       select PCIE_DW
+       select PCIEPORTBUS
+       help
+         Say Y here if you want to enable PCI controller support on Keystone
+         SoCs. The PCI controller on Keystone is based on Designware hardware
+         and therefore the driver re-uses the Designware core functions to
+         implement the driver.
+
+config PCIE_XILINX
+       bool "Xilinx AXI PCIe host bridge support"
+       depends on ARCH_ZYNQ
+       help
+         Say 'Y' here if you want kernel to support the Xilinx AXI PCIe
+         Host Bridge driver.
+
+config PCI_XGENE
+       bool "X-Gene PCIe controller"
+       depends on ARCH_XGENE
+       depends on OF
+       select PCIEPORTBUS
+       help
+         Say Y here if you want internal PCI support on APM X-Gene SoC.
+         There are 5 internal PCIe ports available. Each port is GEN3 capable
+         and have varied lanes from x1 to x8.
+
+config PCI_LAYERSCAPE
+       bool "Freescale Layerscape PCIe controller"
+       depends on OF && ARM
+       select PCIE_DW
+       select MFD_SYSCON
+       help
+         Say Y here if you want PCIe controller support on Layerscape SoCs.
+
 endmenu