PCI: rockchip: Use normal register bank for config accessors

[karo-tx-linux.git] / drivers / pci / host / pcie-rockchip.c

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index 199edd533083c7dcc00cdad043d51dc11e1f1a30..5acf8694fb23bc41d6000c27ae43c425fe478f8a 100644 (file)
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -139,6 +139,7 @@
                 PCIE_CORE_INT_CT | PCIE_CORE_INT_UTC | \
                 PCIE_CORE_INT_MMVC)
 
+#define PCIE_RC_CONFIG_NORMAL_BASE     0x800000
 #define PCIE_RC_CONFIG_BASE            0xa00000
 #define PCIE_RC_CONFIG_RID_CCR         (PCIE_RC_CONFIG_BASE + 0x08)
 #define   PCIE_RC_CONFIG_SCC_SHIFT             16
@@ -301,7 +302,9 @@ static int rockchip_pcie_valid_device(struct rockchip_pcie *rockchip,
 static int rockchip_pcie_rd_own_conf(struct rockchip_pcie *rockchip,
                                     int where, int size, u32 *val)
 {
-       void __iomem *addr = rockchip->apb_base + PCIE_RC_CONFIG_BASE + where;
+       void __iomem *addr;
+
+       addr = rockchip->apb_base + PCIE_RC_CONFIG_NORMAL_BASE + where;
 
        if (!IS_ALIGNED((uintptr_t)addr, size)) {
                *val = 0;
@@ -325,11 +328,13 @@ static int rockchip_pcie_wr_own_conf(struct rockchip_pcie *rockchip,
                                     int where, int size, u32 val)
 {
        u32 mask, tmp, offset;
+       void __iomem *addr;
 
        offset = where & ~0x3;
+       addr = rockchip->apb_base + PCIE_RC_CONFIG_NORMAL_BASE + offset;
 
        if (size == 4) {
-               writel(val, rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset);
+               writel(val, addr);
                return PCIBIOS_SUCCESSFUL;
        }
 
@@ -340,9 +345,9 @@ static int rockchip_pcie_wr_own_conf(struct rockchip_pcie *rockchip,
         * corrupt RW1C bits in adjacent registers.  But the hardware
         * doesn't support smaller writes.
         */
-       tmp = readl(rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset) & mask;
+       tmp = readl(addr) & mask;
        tmp |= val << ((where & 0x3) * 8);
-       writel(tmp, rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset);
+       writel(tmp, addr);
 
        return PCIBIOS_SUCCESSFUL;
 }
@@ -1463,15 +1468,14 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
        if (err)
                goto err_free_res;
 
-       rockchip->msg_region = devm_ioremap(rockchip->dev,
-                                           rockchip->msg_bus_addr, SZ_1M);
+       rockchip->msg_region = devm_ioremap(dev, rockchip->msg_bus_addr, SZ_1M);
        if (!rockchip->msg_region) {
                err = -ENOMEM;
                goto err_free_res;
        }
 
        list_splice_init(&res, &bridge->windows);
-       bridge->dev.parent = &pdev->dev;
+       bridge->dev.parent = dev;
        bridge->sysdata = rockchip;
        bridge->busnr = 0;
        bridge->ops = &rockchip_pcie_ops;