pci: tegra: correctly program PADS_REFCLK registers

[karo-tx-uboot.git] / drivers / pci / pci_tegra.c

diff --git a/drivers/pci/pci_tegra.c b/drivers/pci/pci_tegra.c
index c5b04daffa65cc9b8d698b4d4a7ffa8c1710d05c..1aa56fc9373959dc3fdcec50fb669f1cabc65b28 100644 (file)
--- a/drivers/pci/pci_tegra.c
+++ b/drivers/pci/pci_tegra.c
@@ -154,15 +154,6 @@ DECLARE_GLOBAL_DATA_PTR;
 #define PADS_REFCLK_CFG_PREDI_SHIFT            8  /* 11:8 */
 #define PADS_REFCLK_CFG_DRVI_SHIFT             12 /* 15:12 */
 
-/* Default value provided by HW engineering is 0xfa5c */
-#define PADS_REFCLK_CFG_VALUE \
-       ( \
-               (0x17 << PADS_REFCLK_CFG_TERM_SHIFT)   | \
-               (0    << PADS_REFCLK_CFG_E_TERM_SHIFT) | \
-               (0xa  << PADS_REFCLK_CFG_PREDI_SHIFT)  | \
-               (0xf  << PADS_REFCLK_CFG_DRVI_SHIFT)     \
-       )
-
 #define RP_VEND_XP     0x00000F00
 #define  RP_VEND_XP_DL_UP      (1 << 30)
 
@@ -198,6 +189,8 @@ struct tegra_pcie_soc {
        unsigned int num_ports;
        unsigned long pads_pll_ctl;
        unsigned long tx_ref_sel;
+       u32 pads_refclk_cfg0;
+       u32 pads_refclk_cfg1;
        bool has_pex_clkreq_en;
        bool has_pex_bias_ctrl;
        bool has_cml_clk;
@@ -628,11 +621,9 @@ static int tegra_pcie_phy_enable(struct tegra_pcie *pcie)
        pads_writel(pcie, value, soc->pads_pll_ctl);
 
        /* configure the reference clock driver */
-       value = PADS_REFCLK_CFG_VALUE | (PADS_REFCLK_CFG_VALUE << 16);
-       pads_writel(pcie, value, PADS_REFCLK_CFG0);
-
+       pads_writel(pcie, soc->pads_refclk_cfg0, PADS_REFCLK_CFG0);
        if (soc->num_ports > 2)
-               pads_writel(pcie, PADS_REFCLK_CFG_VALUE, PADS_REFCLK_CFG1);
+               pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1);
 
        /* wait for the PLL to lock */
        err = tegra_pcie_pll_wait(pcie, 500);
@@ -943,6 +934,7 @@ static const struct tegra_pcie_soc pci_tegra_soc[] = {
                .num_ports = 2,
                .pads_pll_ctl = PADS_PLL_CTL_TEGRA20,
                .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10,
+               .pads_refclk_cfg0 = 0xfa5cfa5c,
                .has_pex_clkreq_en = false,
                .has_pex_bias_ctrl = false,
                .has_cml_clk = false,
@@ -952,6 +944,8 @@ static const struct tegra_pcie_soc pci_tegra_soc[] = {
                .num_ports = 3,
                .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
                .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
+               .pads_refclk_cfg0 = 0xfa5cfa5c,
+               .pads_refclk_cfg1 = 0xfa5cfa5c,
                .has_pex_clkreq_en = true,
                .has_pex_bias_ctrl = true,
                .has_cml_clk = true,
@@ -961,6 +955,7 @@ static const struct tegra_pcie_soc pci_tegra_soc[] = {
                .num_ports = 2,
                .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
                .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
+               .pads_refclk_cfg0 = 0x44ac44ac,
                .has_pex_clkreq_en = true,
                .has_pex_bias_ctrl = true,
                .has_cml_clk = true,
@@ -970,6 +965,7 @@ static const struct tegra_pcie_soc pci_tegra_soc[] = {
                .num_ports = 2,
                .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
                .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
+               .pads_refclk_cfg0 = 0x90b890b8,
                .has_pex_clkreq_en = true,
                .has_pex_bias_ctrl = true,
                .has_cml_clk = true,