/*
* Core driver for the imx pin controller
*
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012-2013 Freescale Semiconductor, Inc.
* Copyright (C) 2012 Linaro Ltd.
*
* Author: Dong Aisheng <dong.aisheng@linaro.org>
pin_id = pins[i];
pin_reg = &info->pin_regs[pin_id];
- if (!pin_reg->mux_reg) {
+ if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->mux_reg) {
dev_err(ipctl->dev, "Pin(%s) does not support mux function\n",
info->pins[pin_id].name);
return -EINVAL;
}
- writel(mux[i], ipctl->base + pin_reg->mux_reg);
+ if (info->flags & SHARE_MUX_CONF_REG) {
+ u32 reg;
+ reg = readl(ipctl->base + pin_reg->mux_reg);
+ reg &= ~(0x7 << 20);
+ reg |= (mux[i] << 20);
+ writel(reg, ipctl->base + pin_reg->mux_reg);
+ } else {
+ writel(mux[i], ipctl->base + pin_reg->mux_reg);
+ }
dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%x\n",
pin_reg->mux_reg, mux[i]);
- /* some pins also need select input setting, set it if found */
- if (input_reg[i]) {
+ /*
+ * If the select input value begins with 0xff, it's a quirky
+ * select input and the value should be interpreted as below.
+ * 31 23 15 7 0
+ * | 0xff | shift | width | select |
+ * It's used to work around the problem that the select
+ * input for some pin is not implemented in the select
+ * input register but in some general purpose register.
+ * We encode the select input value, width and shift of
+ * the bit field into input_val cell of pin function ID
+ * in device tree, and then decode them here for setting
+ * up the select input bits in general purpose register.
+ */
+ if (input_val[i] >> 24 == 0xff) {
+ u32 val = input_val[i];
+ u8 select = val & 0xff;
+ u8 width = (val >> 8) & 0xff;
+ u8 shift = (val >> 16) & 0xff;
+ u32 mask = ((1 << width) - 1) << shift;
+ /*
+ * The input_reg[i] here is actually some IOMUXC general
+ * purpose register, not regular select input register.
+ */
+ val = readl(ipctl->base + input_reg[i]);
+ val &= ~mask;
+ val |= select << shift;
+ writel(val, ipctl->base + input_reg[i]);
+ } else if (input_reg[i]) {
+ /*
+ * Regular select input register can never be at offset
+ * 0, and we only print register value for regular case.
+ */
writel(input_val[i], ipctl->base + input_reg[i]);
dev_dbg(ipctl->dev,
"==>select_input: offset 0x%x val 0x%x\n",
const struct imx_pinctrl_soc_info *info = ipctl->info;
const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
- if (!pin_reg->conf_reg) {
+ if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->conf_reg) {
dev_err(info->dev, "Pin(%s) does not support config function\n",
info->pins[pin_id].name);
return -EINVAL;
*config = readl(ipctl->base + pin_reg->conf_reg);
+ if (info->flags & SHARE_MUX_CONF_REG)
+ *config &= 0xffff;
+
return 0;
}
const struct imx_pinctrl_soc_info *info = ipctl->info;
const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
- if (!pin_reg->conf_reg) {
+ if (!(info->flags & ZERO_OFFSET_VALID) && !pin_reg->conf_reg) {
dev_err(info->dev, "Pin(%s) does not support config function\n",
info->pins[pin_id].name);
return -EINVAL;
dev_dbg(ipctl->dev, "pinconf set pin %s\n",
info->pins[pin_id].name);
- writel(config, ipctl->base + pin_reg->conf_reg);
+ if (info->flags & SHARE_MUX_CONF_REG) {
+ u32 reg;
+ reg = readl(ipctl->base + pin_reg->conf_reg);
+ reg &= ~0xffff;
+ reg |= config;
+ writel(reg, ipctl->base + pin_reg->conf_reg);
+ } else {
+ writel(config, ipctl->base + pin_reg->conf_reg);
+ }
dev_dbg(ipctl->dev, "write: offset 0x%x val 0x%lx\n",
pin_reg->conf_reg, config);
* 1 u32 CONFIG, so 24 types in total for each pin.
*/
#define FSL_PIN_SIZE 24
+#define SHARE_FSL_PIN_SIZE 20
static int imx_pinctrl_parse_groups(struct device_node *np,
struct imx_pin_group *grp,
struct imx_pinctrl_soc_info *info,
u32 index)
{
- int size;
+ int size, pin_size;
const __be32 *list;
int i;
u32 config;
dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
+ if (info->flags & SHARE_MUX_CONF_REG)
+ pin_size = SHARE_FSL_PIN_SIZE;
+ else
+ pin_size = FSL_PIN_SIZE;
/* Initialise group */
grp->name = np->name;
*/
list = of_get_property(np, "fsl,pins", &size);
/* we do not check return since it's safe node passed down */
- if (!size || size % FSL_PIN_SIZE) {
+ if (!size || size % pin_size) {
dev_err(info->dev, "Invalid fsl,pins property\n");
return -EINVAL;
}
- grp->npins = size / FSL_PIN_SIZE;
+ grp->npins = size / pin_size;
grp->pins = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
GFP_KERNEL);
grp->mux_mode = devm_kzalloc(info->dev, grp->npins * sizeof(unsigned int),
GFP_KERNEL);
for (i = 0; i < grp->npins; i++) {
u32 mux_reg = be32_to_cpu(*list++);
- u32 conf_reg = be32_to_cpu(*list++);
- unsigned int pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4;
- struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
+ u32 conf_reg;
+ unsigned int pin_id;
+ struct imx_pin_reg *pin_reg;
+ if (info->flags & SHARE_MUX_CONF_REG)
+ conf_reg = mux_reg;
+ else
+ conf_reg = be32_to_cpu(*list++);
+
+ pin_id = mux_reg ? mux_reg / 4 : conf_reg / 4;
+ pin_reg = &info->pin_regs[pin_id];
grp->pins[i] = pin_id;
pin_reg->mux_reg = mux_reg;
pin_reg->conf_reg = conf_reg;
return 0;
}
+
+#ifdef CONFIG_PM
+int imx_pinctrl_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ struct imx_pinctrl *ipctl = platform_get_drvdata(pdev);
+
+ if (!ipctl)
+ return -EINVAL;
+
+ return pinctrl_force_sleep(ipctl->pctl);
+}
+
+int imx_pinctrl_resume(struct platform_device *pdev)
+{
+ struct imx_pinctrl *ipctl = platform_get_drvdata(pdev);
+
+ if (!ipctl)
+ return -EINVAL;
+
+ return pinctrl_force_default(ipctl->pctl);
+}
+#endif
projects / karo-tx-linux.git / blobdiff