#include <linux/string.h>
#include <bcmdefs.h>
#include <osl.h>
-#include <linuxver.h>
+#include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/pci.h>
#include <bcmendian.h>
#include <bcmnvram.h>
#include <sbchipc.h>
+#include <bcmdevs.h>
+#include <sbhndpio.h>
+#include <sbhnddma.h>
#include <wlc_phy_int.h>
#include <wlc_phyreg_n.h>
return NULL;
for (s = vars; s && *s;) {
- if ((bcmp(s, name, len) == 0) && (s[len] == '='))
+ if ((memcmp(s, name, len) == 0) && (s[len] == '='))
return &s[len + 1];
while (*s++)
void write_radio_reg(phy_info_t *pi, u16 addr, u16 val)
{
- osl_t *osh;
+ struct osl_info *osh;
if (NORADIO_ENAB(pi->pubpi))
return;
W_REG(osh, &pi->regs->phy4wdatalo, val);
}
- if (BUSTYPE(pi->sh->bustype) == PCI_BUS) {
+ if (pi->sh->bustype == PCI_BUS) {
if (++pi->phy_wreg >= pi->phy_wreg_limit) {
(void)R_REG(osh, &pi->regs->maccontrol);
pi->phy_wreg = 0;
u16 read_phy_reg(phy_info_t *pi, u16 addr)
{
- osl_t *osh;
+ struct osl_info *osh;
d11regs_t *regs;
osh = pi->sh->osh;
void write_phy_reg(phy_info_t *pi, u16 addr, u16 val)
{
- osl_t *osh;
+ struct osl_info *osh;
d11regs_t *regs;
osh = pi->sh->osh;
#else
W_REG(osh, (volatile u32 *)(®s->phyregaddr),
addr | (val << 16));
- if (BUSTYPE(pi->sh->bustype) == PCI_BUS) {
+ if (pi->sh->bustype == PCI_BUS) {
if (++pi->phy_wreg >= pi->phy_wreg_limit) {
pi->phy_wreg = 0;
(void)R_REG(osh, ®s->phyversion);
void and_phy_reg(phy_info_t *pi, u16 addr, u16 val)
{
- osl_t *osh;
+ struct osl_info *osh;
d11regs_t *regs;
osh = pi->sh->osh;
void or_phy_reg(phy_info_t *pi, u16 addr, u16 val)
{
- osl_t *osh;
+ struct osl_info *osh;
d11regs_t *regs;
osh = pi->sh->osh;
void mod_phy_reg(phy_info_t *pi, u16 addr, u16 mask, u16 val)
{
- osl_t *osh;
+ struct osl_info *osh;
d11regs_t *regs;
osh = pi->sh->osh;
void wlc_phy_shared_detach(shared_phy_t *phy_sh)
{
- osl_t *osh;
+ struct osl_info *osh;
if (phy_sh) {
osh = phy_sh->osh;
u32 sflags = 0;
uint phyversion;
int i;
- osl_t *osh;
+ struct osl_info *osh;
osh = sh->osh;
ASSERT((band == WLC_BAND_2G) || (band == WLC_BAND_5G));
- bzero(channels, sizeof(chanvec_t));
+ memset(channels, 0, sizeof(chanvec_t));
for (i = 0; i < ARRAY_SIZE(chan_info_all); i++) {
channel = chan_info_all[i].chan;
tx_pwr_min = min(tx_pwr_min, tx_pwr_target[rate]);
}
- bzero(pi->tx_power_offset, sizeof(pi->tx_power_offset));
+ memset(pi->tx_power_offset, 0, sizeof(pi->tx_power_offset));
pi->tx_power_max = tx_pwr_max;
pi->tx_power_min = tx_pwr_min;
pi->tx_power_max_rate_ind = tx_pwr_max_rate_ind;
s8 cmplx_pwr_dbm[PHY_CORE_MAX];
u8 i;
- bzero((u8 *) cmplx_pwr_dbm, sizeof(cmplx_pwr_dbm));
+ memset((u8 *) cmplx_pwr_dbm, 0, sizeof(cmplx_pwr_dbm));
ASSERT(pi->pubpi.phy_corenum <= PHY_CORE_MAX);
wlc_phy_compute_dB(cmplx_pwr, cmplx_pwr_dbm, pi->pubpi.phy_corenum);
u8 wait_crs = 0;
u8 i;
- bzero((u8 *) est, sizeof(est));
- bzero((u8 *) cmplx_pwr, sizeof(cmplx_pwr));
- bzero((u8 *) noise_dbm_ant, sizeof(noise_dbm_ant));
+ memset((u8 *) est, 0, sizeof(est));
+ memset((u8 *) cmplx_pwr, 0, sizeof(cmplx_pwr));
+ memset((u8 *) noise_dbm_ant, 0, sizeof(noise_dbm_ant));
log_num_samps = PHY_NOISE_SAMPLE_LOG_NUM_NPHY;
num_samps = 1 << log_num_samps;
u8 idx, core;
ASSERT(pi->pubpi.phy_corenum <= PHY_CORE_MAX);
- bzero((u8 *) cmplx_pwr, sizeof(cmplx_pwr));
- bzero((u8 *) noise_dbm_ant, sizeof(noise_dbm_ant));
+ memset((u8 *) cmplx_pwr, 0, sizeof(cmplx_pwr));
+ memset((u8 *) noise_dbm_ant, 0, sizeof(noise_dbm_ant));
for (idx = 0, core = 0; core < pi->pubpi.phy_corenum; idx += 2, core++) {
lo = wlapi_bmac_read_shm(pi->sh->physhim, M_PWRIND_MAP(idx));