staging: dwc2: simplify register shift expressions

[karo-tx-linux.git] / drivers / staging / dwc2 / core.c

diff --git a/drivers/staging/dwc2/core.c b/drivers/staging/dwc2/core.c
index e3a0e770301d53893cd9aef708972eea0344a99c..04c251c82bc85aec432a4119783ebad9b27c6f49 100644 (file)
--- a/drivers/staging/dwc2/core.c
+++ b/drivers/staging/dwc2/core.c
@@ -90,8 +90,10 @@ static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg)
  */
 static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
 {
-       u32 hs_phy_type = hsotg->hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK;
-       u32 fs_phy_type = hsotg->hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK;
+       u32 hs_phy_type = (hsotg->hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >>
+                         GHWCFG2_HS_PHY_TYPE_SHIFT;
+       u32 fs_phy_type = (hsotg->hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >>
+                         GHWCFG2_FS_PHY_TYPE_SHIFT;
        u32 hcfg, val;
 
        if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
@@ -108,7 +110,7 @@ static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
        dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
        hcfg = readl(hsotg->regs + HCFG);
        hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
-       hcfg |= val;
+       hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT;
        writel(hcfg, hsotg->regs + HCFG);
 }
 
@@ -256,8 +258,10 @@ static void dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
                dwc2_hs_phy_init(hsotg, select_phy);
        }
 
-       hs_phy_type = hsotg->hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK;
-       fs_phy_type = hsotg->hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK;
+       hs_phy_type = (hsotg->hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >>
+                     GHWCFG2_HS_PHY_TYPE_SHIFT;
+       fs_phy_type = (hsotg->hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >>
+                     GHWCFG2_FS_PHY_TYPE_SHIFT;
 
        if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
            fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
@@ -277,20 +281,21 @@ static void dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
 
 static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
 {
-       u32 ahbcfg = 0;
+       u32 ahbcfg = readl(hsotg->regs + GAHBCFG);
 
-       switch (hsotg->hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) {
+       switch ((hsotg->hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >>
+               GHWCFG2_ARCHITECTURE_SHIFT) {
        case GHWCFG2_EXT_DMA_ARCH:
                dev_err(hsotg->dev, "External DMA Mode not supported\n");
                return -EINVAL;
 
        case GHWCFG2_INT_DMA_ARCH:
                dev_dbg(hsotg->dev, "Internal DMA Mode\n");
-               /*
-                * Old value was GAHBCFG_HBSTLEN_INCR - done for
-                * Host mode ISOC in issue fix - vahrama
-                */
-               ahbcfg |= GAHBCFG_HBSTLEN_INCR4;
+               if (hsotg->core_params->ahbcfg != -1) {
+                       ahbcfg &= GAHBCFG_CTRL_MASK;
+                       ahbcfg |= hsotg->core_params->ahbcfg &
+                                 ~GAHBCFG_CTRL_MASK;
+               }
                break;
 
        case GHWCFG2_SLAVE_ONLY_ARCH:
@@ -313,9 +318,6 @@ static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
                hsotg->core_params->dma_desc_enable = 0;
        }
 
-       if (hsotg->core_params->ahb_single > 0)
-               ahbcfg |= GAHBCFG_AHB_SINGLE;
-
        if (hsotg->core_params->dma_enable > 0)
                ahbcfg |= GAHBCFG_DMA_EN;
 
@@ -331,7 +333,8 @@ static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg)
        usbcfg = readl(hsotg->regs + GUSBCFG);
        usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP);
 
-       switch (hsotg->hwcfg2 & GHWCFG2_OP_MODE_MASK) {
+       switch ((hsotg->hwcfg2 & GHWCFG2_OP_MODE_MASK) >>
+               GHWCFG2_OP_MODE_SHIFT) {
        case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
                if (hsotg->core_params->otg_cap ==
                                DWC2_CAP_PARAM_HNP_SRP_CAPABLE)
@@ -602,7 +605,8 @@ void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
        }
 
        if (hsotg->core_params->dma_desc_enable > 0) {
-               u32 op_mode = hsotg->hwcfg2 & GHWCFG2_OP_MODE_MASK;
+               u32 op_mode = (hsotg->hwcfg2 & GHWCFG2_OP_MODE_MASK) >>
+                             GHWCFG2_OP_MODE_SHIFT;
 
                if (hsotg->snpsid < DWC2_CORE_REV_2_90a ||
                    !(hsotg->hwcfg4 & GHWCFG4_DESC_DMA) ||
@@ -1382,14 +1386,14 @@ void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
                dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
                         chan->hc_num);
                dev_vdbg(hsotg->dev, "   Xfer Size: %d\n",
-                        hctsiz >> TSIZ_XFERSIZE_SHIFT &
-                        TSIZ_XFERSIZE_MASK >> TSIZ_XFERSIZE_SHIFT);
+                        (hctsiz & TSIZ_XFERSIZE_MASK) >>
+                        TSIZ_XFERSIZE_SHIFT);
                dev_vdbg(hsotg->dev, "   Num Pkts: %d\n",
-                        hctsiz >> TSIZ_PKTCNT_SHIFT &
-                        TSIZ_PKTCNT_MASK >> TSIZ_PKTCNT_SHIFT);
+                        (hctsiz & TSIZ_PKTCNT_MASK) >>
+                        TSIZ_PKTCNT_SHIFT);
                dev_vdbg(hsotg->dev, "   Start PID: %d\n",
-                        hctsiz >> TSIZ_SC_MC_PID_SHIFT &
-                        TSIZ_SC_MC_PID_MASK >> TSIZ_SC_MC_PID_SHIFT);
+                        (hctsiz & TSIZ_SC_MC_PID_MASK) >>
+                        TSIZ_SC_MC_PID_SHIFT);
        }
 
        if (hsotg->core_params->dma_enable > 0) {
@@ -1433,8 +1437,8 @@ void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
 
        if (dbg_hc(chan))
                dev_vdbg(hsotg->dev, "   Multi Cnt: %d\n",
-                        hcchar >> HCCHAR_MULTICNT_SHIFT &
-                        HCCHAR_MULTICNT_MASK >> HCCHAR_MULTICNT_SHIFT);
+                        (hcchar & HCCHAR_MULTICNT_MASK) >>
+                        HCCHAR_MULTICNT_SHIFT);
 
        writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
        if (dbg_hc(chan))
@@ -1522,8 +1526,8 @@ void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
 
        if (dbg_hc(chan))
                dev_vdbg(hsotg->dev, "   Multi Cnt: %d\n",
-                        hcchar >> HCCHAR_MULTICNT_SHIFT &
-                        HCCHAR_MULTICNT_MASK >> HCCHAR_MULTICNT_SHIFT);
+                        (hcchar & HCCHAR_MULTICNT_MASK) >>
+                        HCCHAR_MULTICNT_SHIFT);
 
        writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
        if (dbg_hc(chan))
@@ -1669,7 +1673,8 @@ u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg)
        if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) &&
            !(usbcfg & GUSBCFG_PHYIF16))
                clock = 60;
-       if ((usbcfg & GUSBCFG_PHYSEL) && (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) ==
+       if ((usbcfg & GUSBCFG_PHYSEL) &&
+           (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >> GHWCFG2_FS_PHY_TYPE_SHIFT ==
            GHWCFG2_FS_PHY_TYPE_SHARED_ULPI)
                clock = 48;
        if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
@@ -1682,14 +1687,15 @@ u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg)
            !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
                clock = 48;
        if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) &&
-           (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) ==
+           (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >> GHWCFG2_FS_PHY_TYPE_SHIFT ==
            GHWCFG2_FS_PHY_TYPE_SHARED_UTMI)
                clock = 48;
-       if ((usbcfg & GUSBCFG_PHYSEL) && (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) ==
+       if ((usbcfg & GUSBCFG_PHYSEL) &&
+           (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >> GHWCFG2_FS_PHY_TYPE_SHIFT ==
            GHWCFG2_FS_PHY_TYPE_DEDICATED)
                clock = 48;
 
-       if ((hprt0 & HPRT0_SPD_MASK) == HPRT0_SPD_HIGH_SPEED)
+       if ((hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT == HPRT0_SPD_HIGH_SPEED)
                /* High speed case */
                return 125 * clock;
        else
@@ -1960,7 +1966,8 @@ int dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val)
        int retval = 0;
        u32 op_mode;
 
-       op_mode = hsotg->hwcfg2 & GHWCFG2_OP_MODE_MASK;
+       op_mode = (hsotg->hwcfg2 & GHWCFG2_OP_MODE_MASK) >>
+                 GHWCFG2_OP_MODE_SHIFT;
 
        switch (val) {
        case DWC2_CAP_PARAM_HNP_SRP_CAPABLE:
@@ -2018,8 +2025,8 @@ int dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val)
        int valid = 1;
        int retval = 0;
 
-       if (val > 0 && (hsotg->hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) ==
-           GHWCFG2_SLAVE_ONLY_ARCH)
+       if (val > 0 && (hsotg->hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >>
+                      GHWCFG2_ARCHITECTURE_SHIFT == GHWCFG2_SLAVE_ONLY_ARCH)
                valid = 0;
        if (val < 0)
                valid = 0;
@@ -2029,8 +2036,8 @@ int dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val)
                        dev_err(hsotg->dev,
                                "%d invalid for dma_enable parameter. Check HW configuration.\n",
                                val);
-               val = (hsotg->hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) !=
-                       GHWCFG2_SLAVE_ONLY_ARCH;
+               val = (hsotg->hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >>
+                     GHWCFG2_ARCHITECTURE_SHIFT != GHWCFG2_SLAVE_ONLY_ARCH;
                dev_dbg(hsotg->dev, "Setting dma_enable to %d\n", val);
                retval = -EINVAL;
        }
@@ -2212,7 +2219,7 @@ int dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val)
                    GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK >>
                                GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT;
 
-       if (val < 15 || val > (1 << (width + 4)))
+       if (val < 15 || val >= (1 << (width + 4)))
                valid = 0;
 
        if (!valid) {
@@ -2279,8 +2286,10 @@ int dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val)
        }
 
 #ifndef NO_FS_PHY_HW_CHECKS
-       hs_phy_type = hsotg->hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK;
-       fs_phy_type = hsotg->hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK;
+       hs_phy_type = (hsotg->hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >>
+                     GHWCFG2_HS_PHY_TYPE_SHIFT;
+       fs_phy_type = (hsotg->hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >>
+                     GHWCFG2_FS_PHY_TYPE_SHIFT;
 
        if (val == DWC2_PHY_TYPE_PARAM_UTMI &&
            (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
@@ -2586,35 +2595,14 @@ int dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val)
        return retval;
 }
 
-int dwc2_set_param_ahb_single(struct dwc2_hsotg *hsotg, int val)
+int dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val)
 {
-       int valid = 1;
-       int retval = 0;
-
-       if (DWC2_PARAM_TEST(val, 0, 1)) {
-               if (val >= 0) {
-                       dev_err(hsotg->dev,
-                               "'%d' invalid for parameter ahb_single\n", val);
-                       dev_err(hsotg->dev, "ahb_single must be 0 or 1\n");
-               }
-               valid = 0;
-       }
-
-       if (val > 0 && hsotg->snpsid < DWC2_CORE_REV_2_94a)
-               valid = 0;
-
-       if (!valid) {
-               if (val >= 0)
-                       dev_err(hsotg->dev,
-                               "%d invalid for parameter ahb_single. Check HW configuration.\n",
-                               val);
-               val = 0;
-               dev_dbg(hsotg->dev, "Setting ahb_single to %d\n", val);
-               retval = -EINVAL;
-       }
-
-       hsotg->core_params->ahb_single = val;
-       return retval;
+       if (val != -1)
+               hsotg->core_params->ahbcfg = val;
+       else
+               hsotg->core_params->ahbcfg = GAHBCFG_HBSTLEN_INCR4 <<
+                                             GAHBCFG_HBSTLEN_SHIFT;
+       return 0;
 }
 
 int dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val)
@@ -2681,7 +2669,7 @@ int dwc2_set_parameters(struct dwc2_hsotg *hsotg,
        retval |= dwc2_set_param_en_multiple_tx_fifo(hsotg,
                        params->en_multiple_tx_fifo);
        retval |= dwc2_set_param_reload_ctl(hsotg, params->reload_ctl);
-       retval |= dwc2_set_param_ahb_single(hsotg, params->ahb_single);
+       retval |= dwc2_set_param_ahbcfg(hsotg, params->ahbcfg);
        retval |= dwc2_set_param_otg_ver(hsotg, params->otg_ver);
 
        return retval;