*/
static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
{
- u32 hs_phy_type = hsotg->hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK;
- u32 fs_phy_type = hsotg->hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK;
+ u32 hs_phy_type = (hsotg->hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >>
+ GHWCFG2_HS_PHY_TYPE_SHIFT;
+ u32 fs_phy_type = (hsotg->hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >>
+ GHWCFG2_FS_PHY_TYPE_SHIFT;
u32 hcfg, val;
if ((hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
hcfg = readl(hsotg->regs + HCFG);
hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
- hcfg |= val;
+ hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT;
writel(hcfg, hsotg->regs + HCFG);
}
dwc2_hs_phy_init(hsotg, select_phy);
}
- hs_phy_type = hsotg->hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK;
- fs_phy_type = hsotg->hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK;
+ hs_phy_type = (hsotg->hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >>
+ GHWCFG2_HS_PHY_TYPE_SHIFT;
+ fs_phy_type = (hsotg->hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >>
+ GHWCFG2_FS_PHY_TYPE_SHIFT;
if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
{
- u32 ahbcfg = 0;
+ u32 ahbcfg = readl(hsotg->regs + GAHBCFG);
- switch (hsotg->hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) {
+ switch ((hsotg->hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >>
+ GHWCFG2_ARCHITECTURE_SHIFT) {
case GHWCFG2_EXT_DMA_ARCH:
dev_err(hsotg->dev, "External DMA Mode not supported\n");
return -EINVAL;
case GHWCFG2_INT_DMA_ARCH:
dev_dbg(hsotg->dev, "Internal DMA Mode\n");
- /*
- * Old value was GAHBCFG_HBSTLEN_INCR - done for
- * Host mode ISOC in issue fix - vahrama
- */
- ahbcfg |= GAHBCFG_HBSTLEN_INCR4;
+ if (hsotg->core_params->ahbcfg != -1) {
+ ahbcfg &= GAHBCFG_CTRL_MASK;
+ ahbcfg |= hsotg->core_params->ahbcfg &
+ ~GAHBCFG_CTRL_MASK;
+ }
break;
case GHWCFG2_SLAVE_ONLY_ARCH:
hsotg->core_params->dma_desc_enable = 0;
}
- if (hsotg->core_params->ahb_single > 0)
- ahbcfg |= GAHBCFG_AHB_SINGLE;
-
if (hsotg->core_params->dma_enable > 0)
ahbcfg |= GAHBCFG_DMA_EN;
usbcfg = readl(hsotg->regs + GUSBCFG);
usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP);
- switch (hsotg->hwcfg2 & GHWCFG2_OP_MODE_MASK) {
+ switch ((hsotg->hwcfg2 & GHWCFG2_OP_MODE_MASK) >>
+ GHWCFG2_OP_MODE_SHIFT) {
case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
if (hsotg->core_params->otg_cap ==
DWC2_CAP_PARAM_HNP_SRP_CAPABLE)
}
if (hsotg->core_params->dma_desc_enable > 0) {
- u32 op_mode = hsotg->hwcfg2 & GHWCFG2_OP_MODE_MASK;
+ u32 op_mode = (hsotg->hwcfg2 & GHWCFG2_OP_MODE_MASK) >>
+ GHWCFG2_OP_MODE_SHIFT;
if (hsotg->snpsid < DWC2_CORE_REV_2_90a ||
!(hsotg->hwcfg4 & GHWCFG4_DESC_DMA) ||
dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
chan->hc_num);
dev_vdbg(hsotg->dev, " Xfer Size: %d\n",
- hctsiz >> TSIZ_XFERSIZE_SHIFT &
- TSIZ_XFERSIZE_MASK >> TSIZ_XFERSIZE_SHIFT);
+ (hctsiz & TSIZ_XFERSIZE_MASK) >>
+ TSIZ_XFERSIZE_SHIFT);
dev_vdbg(hsotg->dev, " Num Pkts: %d\n",
- hctsiz >> TSIZ_PKTCNT_SHIFT &
- TSIZ_PKTCNT_MASK >> TSIZ_PKTCNT_SHIFT);
+ (hctsiz & TSIZ_PKTCNT_MASK) >>
+ TSIZ_PKTCNT_SHIFT);
dev_vdbg(hsotg->dev, " Start PID: %d\n",
- hctsiz >> TSIZ_SC_MC_PID_SHIFT &
- TSIZ_SC_MC_PID_MASK >> TSIZ_SC_MC_PID_SHIFT);
+ (hctsiz & TSIZ_SC_MC_PID_MASK) >>
+ TSIZ_SC_MC_PID_SHIFT);
}
if (hsotg->core_params->dma_enable > 0) {
if (dbg_hc(chan))
dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
- hcchar >> HCCHAR_MULTICNT_SHIFT &
- HCCHAR_MULTICNT_MASK >> HCCHAR_MULTICNT_SHIFT);
+ (hcchar & HCCHAR_MULTICNT_MASK) >>
+ HCCHAR_MULTICNT_SHIFT);
writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
if (dbg_hc(chan))
if (dbg_hc(chan))
dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
- hcchar >> HCCHAR_MULTICNT_SHIFT &
- HCCHAR_MULTICNT_MASK >> HCCHAR_MULTICNT_SHIFT);
+ (hcchar & HCCHAR_MULTICNT_MASK) >>
+ HCCHAR_MULTICNT_SHIFT);
writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
if (dbg_hc(chan))
if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) &&
!(usbcfg & GUSBCFG_PHYIF16))
clock = 60;
- if ((usbcfg & GUSBCFG_PHYSEL) && (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) ==
+ if ((usbcfg & GUSBCFG_PHYSEL) &&
+ (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >> GHWCFG2_FS_PHY_TYPE_SHIFT ==
GHWCFG2_FS_PHY_TYPE_SHARED_ULPI)
clock = 48;
if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
!(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
clock = 48;
if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) &&
- (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) ==
+ (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >> GHWCFG2_FS_PHY_TYPE_SHIFT ==
GHWCFG2_FS_PHY_TYPE_SHARED_UTMI)
clock = 48;
- if ((usbcfg & GUSBCFG_PHYSEL) && (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) ==
+ if ((usbcfg & GUSBCFG_PHYSEL) &&
+ (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >> GHWCFG2_FS_PHY_TYPE_SHIFT ==
GHWCFG2_FS_PHY_TYPE_DEDICATED)
clock = 48;
- if ((hprt0 & HPRT0_SPD_MASK) == HPRT0_SPD_HIGH_SPEED)
+ if ((hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT == HPRT0_SPD_HIGH_SPEED)
/* High speed case */
return 125 * clock;
else
int retval = 0;
u32 op_mode;
- op_mode = hsotg->hwcfg2 & GHWCFG2_OP_MODE_MASK;
+ op_mode = (hsotg->hwcfg2 & GHWCFG2_OP_MODE_MASK) >>
+ GHWCFG2_OP_MODE_SHIFT;
switch (val) {
case DWC2_CAP_PARAM_HNP_SRP_CAPABLE:
int valid = 1;
int retval = 0;
- if (val > 0 && (hsotg->hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) ==
- GHWCFG2_SLAVE_ONLY_ARCH)
+ if (val > 0 && (hsotg->hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >>
+ GHWCFG2_ARCHITECTURE_SHIFT == GHWCFG2_SLAVE_ONLY_ARCH)
valid = 0;
if (val < 0)
valid = 0;
dev_err(hsotg->dev,
"%d invalid for dma_enable parameter. Check HW configuration.\n",
val);
- val = (hsotg->hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) !=
- GHWCFG2_SLAVE_ONLY_ARCH;
+ val = (hsotg->hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >>
+ GHWCFG2_ARCHITECTURE_SHIFT != GHWCFG2_SLAVE_ONLY_ARCH;
dev_dbg(hsotg->dev, "Setting dma_enable to %d\n", val);
retval = -EINVAL;
}
GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK >>
GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT;
- if (val < 15 || val > (1 << (width + 4)))
+ if (val < 15 || val >= (1 << (width + 4)))
valid = 0;
if (!valid) {
}
#ifndef NO_FS_PHY_HW_CHECKS
- hs_phy_type = hsotg->hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK;
- fs_phy_type = hsotg->hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK;
+ hs_phy_type = (hsotg->hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >>
+ GHWCFG2_HS_PHY_TYPE_SHIFT;
+ fs_phy_type = (hsotg->hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >>
+ GHWCFG2_FS_PHY_TYPE_SHIFT;
if (val == DWC2_PHY_TYPE_PARAM_UTMI &&
(hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
return retval;
}
-int dwc2_set_param_ahb_single(struct dwc2_hsotg *hsotg, int val)
+int dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val)
{
- int valid = 1;
- int retval = 0;
-
- if (DWC2_PARAM_TEST(val, 0, 1)) {
- if (val >= 0) {
- dev_err(hsotg->dev,
- "'%d' invalid for parameter ahb_single\n", val);
- dev_err(hsotg->dev, "ahb_single must be 0 or 1\n");
- }
- valid = 0;
- }
-
- if (val > 0 && hsotg->snpsid < DWC2_CORE_REV_2_94a)
- valid = 0;
-
- if (!valid) {
- if (val >= 0)
- dev_err(hsotg->dev,
- "%d invalid for parameter ahb_single. Check HW configuration.\n",
- val);
- val = 0;
- dev_dbg(hsotg->dev, "Setting ahb_single to %d\n", val);
- retval = -EINVAL;
- }
-
- hsotg->core_params->ahb_single = val;
- return retval;
+ if (val != -1)
+ hsotg->core_params->ahbcfg = val;
+ else
+ hsotg->core_params->ahbcfg = GAHBCFG_HBSTLEN_INCR4 <<
+ GAHBCFG_HBSTLEN_SHIFT;
+ return 0;
}
int dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val)
retval |= dwc2_set_param_en_multiple_tx_fifo(hsotg,
params->en_multiple_tx_fifo);
retval |= dwc2_set_param_reload_ctl(hsotg, params->reload_ctl);
- retval |= dwc2_set_param_ahb_single(hsotg, params->ahb_single);
+ retval |= dwc2_set_param_ahbcfg(hsotg, params->ahbcfg);
retval |= dwc2_set_param_otg_ver(hsotg, params->otg_ver);
return retval;